Powerchip Semiconductor Corporation

Leo Wang

Saysamone Pittikoun

Chien-Chih Du

Chen-Chiu Hsue

Cheng-Tung Huang

Da Sung

A flash memory cell including a first conductive type substrate, a second conductive type well, a patterned film layer, a second conductive type doped region, a tunneling dielectric layer, a plurality of floating gates, an inter-gate dielectric layer and a plurality of control gates is provided. The floating gates are formed on the first conductive type substrate outside the patterned film layer. The floating gates have a thickness greater than the patterned film layer. Thus, the overlapping area between the floating gates and the control gates and hence the coupling ratio of the flash memory cell is increased.

Fabricating method of a flash memory cell

A flash memory cell including a p-type substrate, an n-type deep well, a stacked gate structure, a source region, a drain region, a p-type pocket doped region, spacers, a p-type doped region and a contact plug is provided. The n-type deep well is set up within the p-type substrate and the stacked gate structure is set up over the p-type substrate. The stacked gate structure further includes a tunneling oxide layer, a floating gate, an inter-gate dielectric layer, a control gate and a cap layer sequentially formed over the p-type substrate. The source region and the drain region are set up in the p-type substrate on each side of the stacked gate structure. The p-type pocket doped region is set up within the n-type deep well region and extends from the drain region to an area underneath the stacked gate structure adjacent to the source region. The spacers are attached to the sidewalls of the stacked gate structure. The p-type doped region is set up within the drain region. The p-type doped region passes through the junction between the drain region and the p-type pocket doped region but is separated from the spacer by a distance. The contact plug is set up over the drain region and is electrically connected to the p-type doped region.

Flash memory cell and manufacturing method thereof

Flash memory cell

A method of fabricating a flash memory is provided. A substrate having several device isolation structures for defining an active region is provided. A tunneling dielectric layer and a patterned mask layer are formed over the active region. A portion of each device isolation structure is removed to form a plurality of trenches. A dielectric layer is formed over the substrate and a sacrificial layer is filled the trenches. A portion of the dielectric layer is removed using the sacrificial layer as a self-aligned mask. The patterned mask layer is removed and a conductive layer that exposed the top section of the sacrificial layers is formed over the substrate. After removing the sacrificial layer, an inter-gate dielectric layer and a control gate are formed over the substrate. A source region and a drain region are formed in the substrate on each side of the control gate.

Method of fabricating a flash memory

A method of fabricating a flash memory is provided. A substrate having several device isolation structures for defining an active region is provided. A tunneling dielectric layer and a patterned mask layer are sequentially formed over the active region of the substrate. A sacrificial layer is formed on the substrates. Thereafter, the sacrificial layer is patterned to retain a part of sacrificial layer on the device isolation structures. The patterned mask layer is removed, and a conductive layer that exposed the top section of the sacrificial layers is formed over the substrate. After removing the sacrificial layer, an inter-gate dielectric layer is formed over the substrate. A control gate is formed over the inter-gate dielectric layer. Finally, a source region and a drain region are formed in the substrate on each side of the control gate.

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Hsinchu, Taiwan

Leo Wang