Datatape Incorporated

Other

Leo T Van Lahr

Charles Darwin Snelling

Robert R Bielby

Levi H Robinson

Richard L Couchman

The liquid level detector system of the present invention comprises a heater thermally coupled to the interior of the vessel. A linear sensor, having a vertical longitudinal axis, is located in proximity to the heater such that discrete elevations of the interior of the vessel are thermally coupled to corresponding longitudinal portions of the sensor. The correspondence is incrementally continuous such that the elevations corresponding to the portions of the sensor increase from one to the other end of the sensor. The sensor may be actuated resulting in a resistance measurement indicative of the temperature detected by it. The vertical dimension of the sensor is sufficiently large such that the resistance measurement will vary in proportion to the longitudinal portion of the sensor thermally coupled to the liquid. The sensor generates an electrical signal defining a temperature signal indicative of the resistance measurement and thereby the temperature detected by the sensor. A processor is electrically connected to the sensor for receiving and measuring the temperature signal after actuation of the heater. The processor is programmed to use the temperature signal to calculate the elevation of the upper surface of the liquid in the vessel.

Apparatus for detecting the internal liquid level in a vessel

A digital data synchronizer, synchronizes a digital data system to an incoming serial bit stream having a segment of pseudo random bit sequence, which is a function of a predetermined primitive polynomial, preceeding the start of data. The synchronizer includes a first feedback shift register configured as a multiplier for generating the pseudo random bit sequence. The multiplier register operates on the incoming serial bit stream to determine whether a valid bit sequence of the primitive polynomial is present in the incoming serial bit stream, and if it is, a zero output is produced. A second feedback shift register configured as a divider produces a pseudo random bit sequence which is also a function of the predetermined primitive polynomial. A counter is provided to monitor the number of zeros outputted by the multiplier feedback shift register. When a preset count is reached, the contents of the multiplier shift register is parallel loaded into the divider shift register if the bit sequence of the divider shift register does not match the bit sequence of the incoming serial data. Thus, the divider pseudo random sequence is synchronized to the incoming serial data. A synch word detector monitors the parallel contents of the divider register. When the synch word detector detects a predetermined word in the pseudo random bit sequence produced by the divider, it produces an output flag which indicates the next bit in the incoming digital data word is the first data bit.

Digital data synchronizer

Apparatus for enhancing the bit error rate performance of a storage medium, such as magnetic tape, magnetic disk, optical disk, or an equivalent thereof, includes two data transmission channels for recording in duplicate a stream of data bits corresponding to an information-bearing signal, each recorded bit stream being potentially influenced by a pattern of statistically distributed recording surface defects. During playback, error detection and correction circuitry for each channel provides an alarm signal synchronized with each uncorrected error condition in the corresponding stream of playback bits. A control circuit, responsive to the alarm signals from each channel, serves to interleave error-free bits from one channel, to the exclusion of error bits from the other channel, to provide a single continuous stream of relatively error-free bits corresponding to the information-bearing signal recorded.

Growing community of inventors

Glendora, CA, United States of America

Leo T Van Lahr