Freescale Semiconductor,inc.

Motorola Corporation

Astrowatt, Inc.

Applied Novel Devices, Inc.

University of Florida Research Foundation, Incorporated

Freescale Semiconductors Inc.

Leo Mathew

Ramachandran Muralidhar

Rajesh A Rao

Vishal P Trivedi

Bich-Yen Nguyen

Voon-Yew Thean

Tab Allen Stephens

Dharmesh Jawarani

James David Burnett

Byoung W Min

Rode R Mora

Yang Du

Michael G Khazhinsky

Mohamed S Moosa

Sriram Kalpat

Michael Alan Sadd

Tushar Praful Merchant

David C Sing

Marius K Orlowski

Ted R White

Robert F Steimle

Bruce E White

Venkat Kolagunta

John R Alvis

Daniel Fine

John E Moore

Jerry G Fossum

Michael G Harrison

Anne M Vandooren

Prasad Venkatraman

Mariam G Sadaka

Hector Adrian Sanchez

James W Miller

Alexander Barr

Varughese Mathew

Jeffrey Pearse

Zhonghai Shi

Tien Ying Luo

Brian J Goolsby

Veeraraghavan Dhandapani

Keith G Kamekona

Ross Edward Noble

Daniel T Pham

Daniel Thanh-Khac Pham

Surya Veeraraghavan

John J Hackenberg

Raghaw S Rai

Anne Vandooren

Lakshmanna Vishnubholta

Lixin Ge

Byoung L Min

Huy Trong Tran

Daniel G Tekleab

A method of fabricating an electronic device can include forming a plurality of vertical channels having sidewalls over a substrate, and forming gate dielectric regions over portions of the vertical channels and planar regions adjoining the vertical channels. Gate electrode regions are then formed over portions of the gate dielectric regions. The gate electrode material and the vertical channel region are doped and sized to enable full depletion of charges during operation. Source and body tie regions are formed on the vertical sidewalls by doping with a p-type or n-type dopant. Dielectric regions over the gate electrode regions are formed to electrically isolate the gate electrode regions from the source regions. A metallic layer is formed over the first side of the substrate having the vertical channels. Stress is then induced within the substrate by annealing and/or cooling to separate a semiconductor region of the substrate and the metallic layer from the remaining portion of the substrate. Drain electrode contacts are formed over the semiconductor region while gate electrode and source electrode contacts are formed by etching portions of a metallic layer formed over the first side of the substrate.

Structures and methods of fabricating electronic devices using separation and charge depletion techniques

A method for making a semiconductor device is provided. The method includes forming a first transistor with a vertical active region and a horizontal active region extending on both sides of the vertical active region. The method further includes forming a second transistor with a vertical active region. The method further includes forming a third transistor with a vertical active region and a horizontal active region extending on only one side of the vertical active region.

Multiple device types including an inverted-T channel transistor and method therefor

A method for forming a phase change memory cell (PCM) includes forming a heater for the phase change memory and forming a phase change structrure electrically coupled to the heater. The forming a heater includes siliciding a material including silicon to form a silicide structure, wherein the heater includes at least a portion of the silicide structure. The phase change structure exhibits a first resistive value when in a first phase state and exhibits a second resistive value when in a second phase state. The silicide structure produces heat when current flows through the silicide structure for changing the phase state of the phase change structure.

Phase change memory cell with heater and method therefor

A phase change memory (PCM) cell includes a transistor, a PCM structure, and a heater. The transistor has a first current electrode and a second current electrode in a structure, and a channel region having a first portion along a first sidewall of the structure and having a second portion along a second sidewall of the structure. The second sidewall is opposite the first sidewall. The transistor has a control electrode that has a first portion adjacent to the first sidewall and a second portion adjacent to the second sidewall. The PCM structure exhibits first and second resistive values when in first and second phase states, respectively. The heater is on the structure and produces heat when current flows through the heater for changing the phase state of the phase change structure.

Method of making a phase change memory cell having a silicide heater in conjunction with a FinFET

A method for creating an inverse T field effect transistor is provided. The method includes creating a horizontal active region and a vertical active region on a substrate. The method further comprises forming a sidewall spacer on a first side of the vertical active region and a second side of the vertical active region. The method further includes removing a portion of the horizontal active region, which is not covered by the sidewall spacer. The method further includes removing the sidewall spacer. The method further includes forming a gate dielectric over at least a first part of the horizontal active region and at least a first part of the vertical active region. The method further includes forming a gate electrode over the gate dielectric. The method further includes forming a source region and a drain region over at least a second part of the horizontal active region and at least a second part of the vertical active region.

Method of making an inverted-T channel transistor

Embodiments relate to a two-transistor (2T) floating-body cell (FBC) for embedded-DRAM applications. Further embodiments pertain to a floating-body/gate cell (FBGC), which yields reduction in power dissipation, in addition to better signal margin, longer data retention, and higher memory density.

Two-transistor floating-body dynamic memory cell

A method for making a transistor is provided which comprises (a) providing a semiconductor structure having a gate () overlying a semiconductor layer (), and having at least one spacer structure () disposed adjacent to said gate; (b) removing a portion of the semiconductor structure adjacent to the spacer structure, thereby exposing a portion () of the semiconductor structure which underlies the spacer structure; and (c) subjecting the exposed portion of the semiconductor structure to an angled implant ().

Method to improve source/drain parasitics in vertical devices

An integrated circuit includes a logic circuit and a memory cell. The logic circuit includes a P-channel transistor, and the memory cell includes a P-channel transistor. The P-channel transistor of the logic circuit includes a channel region. The channel region has a portion located along a sidewall of a semiconductor structure having a surface orientation of (110). The portion of the channel region located along the sidewall has a first vertical dimension that is greater than a vertical dimension of any portion of the channel region of the P-channel transistor of the memory cell located along a sidewall of a semiconductor structure having a surface orientation of (110).

Integrated circuit using FinFETs and having a static random access memory (SRAM)

A method of forming an electronic device can include forming a patterned layer adjacent to a side of a substrate including a semiconductor material. The method can also include separating a semiconductor layer and the patterned layer from the substrate, wherein the semiconductor layer is a portion of the substrate.

Method of forming an electronic device using a separation technique

A method for forming a phase change memory cell (PCM) includes forming a heater for the phase change memory and forming a phase change structure electrically coupled to the heater. The forming a heater includes siliciding a material including silicon to form a silicide structure, wherein the heater includes at least a portion of the silicide structure. The phase change structure exhibits a first resistive value when in a first phase state and exhibits a second resistive value when in a second phase state. The silicide structure produces heat when current flows through the silicide structure for changing the phase state of the phase change structure.

A semiconductor fabrication process includes forming a gate electrode () overlying a gate dielectric () overlying a semiconductor substrate () of a wafer () and a liner dielectric layer () including vertical portions () adjacent sidewalls of the gate electrode and horizontal portions () overlying an upper surface of the semiconductor substrate (). A spacer () is formed adjacent a vertical portion () and overlying a horizontal portion () of the liner dielectric layer (). After forming the spacer (), exposed portions of the liner dielectric layer () are removed to form a liner dielectric structure () covered by the extension spacer (). The extension spacer () is then etched back to expose or uncover extremities of the liner dielectric structure (). Prior to etching back the spacer (), a metal () may be sputtered deposited over the wafer () preparatory to forming a silicide (). After the etch back the wafer () may be dipped in piranha solution and cleaned with an RF sputter () of argon.

Semiconductor fabrication process including silicide stringer removal processing

A method for processing a substrate comprising at least a buried oxide (BOX) layer and a semiconductor material layer is provided. The method includes etching the semiconductor material layer to form a vertical semiconductor material structure overlying the BOX layer, leaving an exposed portion of the BOX layer. The method further includes exposing a top surface of the exposed portion of the BOX layer to an oxide etch resistant species to form a thin oxide etch resistant layer overlying the exposed portion of the BOX layer.

Method of forming a finFET and structure

Forming structures such as fins in a semiconductor layer according to a pattern formed by oxidizing a sidewall of a layer of oxidizable material. In one embodiment, source/drain pattern structures and a fin pattern structures are patterned in the oxidizable layer. The fin pattern structure is then masked from an oxidation process that grows oxide on the sidewalls of the channel pattern structure and the top surface of the source/drain pattern structures. The remaining oxidizable material of the channel pattern structure is subsequently removed leaving a hole between two portions of the oxide layer. These two portions are used in one embodiment as a mask for patterning the semiconductor layer to form two fins. This patterning also leaves the source/drain structures connected to the fins.

Semiconductor structure pattern formation

A semiconductor device has a semiconductor substrate that in turn has a top semiconductor layer portion and a major supporting portion under the top semiconductor layer portion. An interconnect layer is over the semiconductor layer. A memory array is in a portion of the top semiconductor layer portion and a portion of the interconnect layer. The memory is erased by removing at least a portion of the major supporting portion and, after the step of removing, applying light to the memory array from a side opposite the interconnect layer. The result is that the memory array receives light from the backside and is erased.

Light erasable memory and method therefor

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Austin, TX, United States of America

Leo Mathew