Marvell Asia Pte., Ltd.

National Semiconductor Corporation

Marvellworld Trade Ltd.

Leo Jiang

Mats Oberg

Nedeljko Varnica

Noam Mizrahi

Konstantin Kudryavtsev

Christophe Therene

Manish Shrivastava

Nitin Nangare

Kenneth C Ma

Scott Shaw

Ruwan Ratnayake

Igor Polivanyi

Vimi Pandey

Wen Lung Chang

Quynh Chau

Embodiments described herein provide improved methods and systems for generating metadata for media objects at a computational engine (such as an artificial intelligence engine) within the storage edge controller, and for storing and using such metadata, in data processing systems.

Storage edge controller with a metadata computational engine

A storage control device coupled to a storage device and located remotely from a host device receives media object data from the host device. The storage control device identifies a type of the media object data and select, based on the identified type, a computational model from among a plurality of computational models for use by a computational engine of the storage control device. The computational engine uses the selected computational model to generate metadata describing the media object data. The metadata is stored in the storage device so as to be selectively retrievable from the storage device separately from the media object data.

Systems and methods for generating metadata describing unstructured data objects at the storage edge

A method and apparatus is disclosed for controlling the application of a clock stopping signal in a processor to limit power consumption. The system controller receives addresses, signals indicative of primary and secondary system activity, and at least one nap timeout signal. Interrupt addresses or programmed addresses are trapped and stored as shadowed addresses. Current addresses may be compared with shadowed addresses. Matching addresses trigger a nap mode. Upon nap mode triggering, the clock stopping signal may be applied during a throttling period. Applying the clock stopping signal with programmable duty cycle during the throttling period ensures that processing necessary for the detection and servicing of primary and secondary activity can occur. A prefetch detect circuit ensures that shadowed addresses loaded in the middle of a prefetch do not trigger the clock stopping signal. Clock stopping signal is removed or inhibited when primary or secondary activity is detected or when a nap timer expires.

Power conservation method and apparatus activated by detecting shadowed

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Fremont, CA, United States of America

Leo Jiang