Cypress Semiconductor Corporation

Leo F Luquette, Jr

Andrew J Walker

Roger J Bettman

Marc D Hartranft

Sungkwon Lee

Sai Prashanth Dhanraj

Dung Ho

Gina Liao

Iman Rezanezhad Gatabi

Scott Ward

An ESD device that includes a gate and an n-drain region isolated from the gate and formed at least partially within an n-well region, which in turn is formed at least partially within a deep n-well region. The doping levels of the n-drain region, the n-well region and the deep n-well region are in a descending order. The ESD device has trigger and holding voltages, above the operation voltage of its protected circuit, which are layout-configurable by altering the distance between the n-drain and a side edge of the n-well region.

ESD clamp with a layout-alterable trigger voltage and a holding voltage above the supply voltage

A method and apparatus to provide electrostatic discharge (ESD) protection to electronic circuits using a combination of low voltage and high voltage transistors.

Cascode combination of low and high voltage transistors for electrostatic discharge circuit

Growing community of inventors

Monument, CO, United States of America

Leo F Luquette, Jr