International Business Machines Corporation

Leo A Noel

Anne Elizabeth Gattiker

Donald Lawrence Wheater

Jeffrey H Dreibelbis

Phillip J Nigh

Jody John Van Horn

Luke D Lacroix

Raymond J Bulaga

Rex Ngo Kho

John L Harris

William J Thibault

A method and system are provided that minimize wafer or package level test time without adversely impacting yields in downstream manufacturing processes or degrading outgoing quality levels. The method provides optimization by determining, a priority, the most effective set of tests for a given lot or wafer. The invention implements a method using a processor-based system involving the integration of multiple sources of data that include: historical and realtime, product specific and lot specific, from wafer fabrication data (i.e., process measurements, defect inspections, and parametric testing), product qualification test results, physical failure analysis results and manufacturing functional test results. These various forms of data are used to determine an optimal set of tests to run using a test application sequence, on a given product to optimize test time with minimum risk to yield or product quality.

Method for test optimization using historical and actual fabrication test data

A method for testing high I/O chips on low I/O testers is provided. Chips having programmable I/Os are used with an interface board that shorts groups of I/Os to a single tester channel. Patterns are provided to the chip to enable one I/O of each group at a time, thereby allowing all I/Os in each group to be tested sequentially. Thus, a multiplexing function is divided between the chip itself and the interface board.

Testing high I/O integrated circuits on a low I/O tester

A device for testing the fixability of logic circuits having an embedded memory. The logic circuit includes a built-in test circuit for generating data which tests the embedded memory. An allocation logic circuit provides an output line for each bit of the memory identifying if the bit has either failed or passed. A Failed Data Bit Register is connected to the output lines. The Failed Data Bit Register includes a plurality of shift register stages. A multiplex circuit associated with each stage of the shift register receives as a first input the corresponding output line of the allocation logic circuit. A second input of the multiplex circuit connects to the preceding stage of the shift register. A clock cycle counter connects to an enabling line of the multiplex circuits and to a source of clock pulses. The clock cycle counter enables the plurality of multiplex circuits to cycle data from the allocation logic circuit through the plurality of stages until it is completely cycled through the plurality of stages. A fail counter is connected to the last stage and counts the number of times Failed Data Bits have been produced by recycling the data.

Device for indicating the fixability of a logic circuit

A method of dynamically modifying a test program makes testing more efficient and less costly while avoiding errors from manual operations. In one embodiment the order of functional tests in the test program is dynamically changed based on the results of testing. Tests that have caused fails are moved earlier in the testing program without having to recompile the test program. Each functional test has an initialization step to set the chip in a state from which subsequent test vectors are run.

Dynamic test reordering

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Essex Junction, VT, United States of America

Leo A Noel