Stats Chippac Pte. Ltd.

St Assembly Test Services Inc.

Leo A Merilo

Emmanuel Espiritu

Dario S Filoteo, Jr

Rachel Layda Abinan

Philip Lyndon Cablao

Allan Pumatong Ilagan

Il Kwon Shim

Virgil Cotoco Ararao

Hermes T Apale

Dario Filoteo

Philip Lyndon R Cablao

Weddie Pacio Aquien

Weddle Aquien

A semiconductor package includes a ball grid array (BGA) substrate having integrated metal layer circuitry, a flip chip chip scale module package (CSMP) having a first integrated passive device (IPD), the flip chip chip scale module package attached to the BGA substrate, and an application die attached to the IPD. A method of manufacturing a semiconductor package includes providing a BGA substrate having integrated metal layer circuitry, attaching a flip chip CSMP having a first IPD to the BGA substrate, and attaching an application die to the IPD.

Chip scale module package in BGA semiconductor package

An integrated circuit package system includes providing a substrate having an integrated circuit, attaching a heatspreader having a force control protrusion on the substrate, and forming an encapsulant over the heatspreader and the integrated circuit.

Integrated circuit package system with heatspreader

An integrated circuit package system is provided forming an integrated circuit die having a first bond pad provided thereon, forming an interconnect stack on a first external interconnect, and connecting the interconnect stack to the first bond pad.

Integrated circuit package system having interconnect stack and external interconnect

A semiconductor package includes a leadframe having first and second level downset lead extensions, a quad flat nonleaded package (QFN) attached to the first level downset lead extension, and a flip chip die attached to the second level downset lead extension. Another embodiment of a semiconductor package includes a leadframe having a lead, a first quad flat nonleaded package (QFN) connected to the lead, and a second quad flat nonleaded package invertly connected to a top surface of the first quad flat nonleaded package, wherein the second quad flat nonleaded package is wirebonded to the lead. A third embodiment of a semiconductor package includes a leadframe having a lead with a first level downset lead extension, a quad flat nonleaded package (QFN) connected to the first level downset lead extension, and a first wirebondable die attached to a top or bottom surface of the quad flat nonleaded package.

Method of forming quad flat package

Quad flat package

A stacked integrated circuit package system is provided forming a first stack layer having a first integrated circuit die on a first substrate, forming a second stack layer having a second integrated circuit die on a second substrate, and mechanically and electrically connecting a spacer layer having a first passive component between the second stack layer and the first stack layer.

Stacked integrated circuits package system with passive components

A stacked die semiconductor package includes a first integrated circuit chip, a first circuit tape coupled to the first integrated circuit chip, a second integrated circuit chip coupled to the first circuit tape, and at least one component coupled to the first circuit tape. The at least one component may include one or more passive components, one or more active components, or a combination of passive and active components. The stacked die semiconductor package can also include a second circuit tape coupled to the second integrated circuit chip and a third integrated circuit chip coupled to the second circuit tape. The stacked die semiconductor package can also include an encapsulant.

Stacked die semiconductor device having circuit tape

An integrated circuit package-in-package system is provided including forming an external interconnect having an upper portion and a lower portion; forming a packaged device; mounting an active device over the packaged device; connecting the active device to the packaged device and the upper portion; and molding the packaged device, the active device, and the upper portion.

Integrated circuit package-in-package system

A method and assembly are provided for anchoring the heat spreader of a PBGA package to the substrate thereof as part of the PBGA package. These anchor features are provided over the surface of the substrate of the PBGA package. The anchor features align with openings created in the heat spreader stand-off, thus allowing for quick and reliable positioning and anchoring of the heat spreader over the surface of the substrate of the package.

Heat spreader anchoring and grounding method and thermally enhanced PBGA package using the same

A new method and assembly are provided for anchoring the heat spreader of a PBGA package to the substrate thereof. Anchor features are made part of the PBGA package. These anchor features are provided over the surface of the substrate of the PBGA package. The anchor features align with openings created in the heat spreader stand-off, thus allowing for quick and reliable positioning and anchoring of the heat spreader over the surface of the substrate of the package.

Growing community of inventors

Singapore, Singapore

Leo A Merilo