University of Southern California

Lena Peterson

William C Athas

Nestor Tzartzanis

Weihua Mao

High performance clock-powered logic runs at below supply levels and reduces the need for faster digital logic circuitry. In a preferred embodiment, a clocked buffer is used to drive the signal line. The receiving end of the line is connected to a jam latch, preferably followed by an n-latch, followed by the digital logic, and followed by a second n-latch. The first n-latch is eliminated in an alternate embodiment, preferably one that uses complementary data signals.

High performance clock-powered logic

High performance clock-powered logic runs at below supply levels and reduces the need for faster digital logic circuitry. In a preferred embodiment, a clocked buffer () is used to drive the signal line. The receiving end of the line is connected to a jam latch (), preferably followed by an n-latch (), followed by the digital logic (), and followed by a second n-latch (). The first n-latch is eliminated in an alternative embodiment, preferably one that uses complementary data signals.

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Gothenburg, Sweden

Lena Peterson