Intel Corporation

Len J Schultz

William S Wu

Nhon Toai Quach

Stephen S Pawlowski

Peter D MacWilliams

Dean A Mulla

Muthurajan Jayakumar

John Wai Fu

Jim Hays

Processor implementation-specific instructions save a processor state in a system memory and attempt to correct the error. Control is then transferred to processor-independent instructions. Control is returned to the processor implementation-specific instructions which then return to an interrupted context of the processor by restoring the processor state.

Method of correcting a machine check error

A method of handling memory errors. A memory fault indication is received that is true if an error in the memory is detected while executing a memory load request to retrieve a value from the memory. A speculative load indication is received that is true if the memory load request was issued speculatively. If the memory fault indication is true and the speculative load indication is true, then an error indication that the returned value is invalid is provided, otherwise, error recovery is performed.

Error recovery for speculative memory accesses

A method for handling different of types of data bit errors in a computer system. In one embodiment, the method comprises the step of storing a data line in a first storage location. The method also includes the step of retrieving the data line from the first storage location. Data bit errors in the data line are detected and the data line is marked as containing a data bit error and stored in a storage location if the data line is not to be used immediately by a requesting process; otherwise error handling is performed by halting the requesting process.

Method and apparatus for fault on use data error handling

A method and device for tracking a bus transaction between first and second agents coupled to a bus includes issuing a request for the transaction by the first agent, storing information regarding the transaction in a buffer, and deleting the information regarding the transaction from the buffer if the first agent receives an indication that the second agent will not issue a retry.

Method and apparatus for tracking bus transactions

A method and apparatus for transferring data between bus agents in a computer system including a bus operating at a bus clock rate. The method includes the step of receiving a transaction request from a requesting agent including an indication of a plurality of data widths the requesting agent processes. In response to the transaction request, a data transmission is configured in accordance with a data width that both the requesting agent and a responding agent process. The data transmission is performed asynchronously with respect to the bus clock if the data width is one of a first plurality of data widths, otherwise, the data transmission is performed synchronously with respect to the bus clock.

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San Jose, CA, United States of America

Len J Schultz