Entorian Technologies LP

Johnson Controls Tyco IP Holdings Llp

Staktek Group L.p.

Leland Szewerenko

Julian Partridge

James Douglas Wehrly, Jr

Ron Orris

David Roper

Paul Goodwin

Tim Roy

Joe Villani

Roel Perez

Thomas Branca

Wayne Lieberman

The present disclosure relates to a method for determining an efficiency curve of a chiller that includes operating a chiller over a range of operating capacities, measuring a temperature of water entering the chiller at an initial capacity, measuring a temperature of water exiting the chiller at the initial capacity, measuring a power consumption of the chiller at the initial capacity, calculating an initial efficiency of the chiller at the initial capacity, measuring a plurality of temperatures of water entering the chiller at a plurality of capacities, measuring a plurality of temperatures of water exiting the chiller at each of the plurality of capacities, measuring a plurality of power consumptions at each of the plurality of capacities, calculating a plurality of efficiencies at each of the plurality of capacities, and generating an efficiency curve for the chiller with the initial efficiency and the plurality of efficiencies.

System and method for determining efficiency of chillers

A flash memory system having the capability of streaming data directly from flash memory to the interface of a host computer in order to substantially reduce latency of to-host transfers, while also maintaining the capabilities for caching and overlapped flash I/O provided by RAM DMA transfers. When data is read from the flash memory, the data is transferred into the RAM buffer and at the option of the memory controller, directly (via an intermediate FIFO) to the host interface. This results in a desirable reduction in the latency of data transfer because as soon as the first byte of data is read from the flash memory by the DMA engine, the data will be transferred directly to the host interface. Because the data is also being transferred to the buffer RAM, preferred embodiments of the present invention still provide the advantages of using an intermediate transfer buffer.

System and method for reduced latency data transfers from flash memory to host by utilizing concurrent transfers into RAM buffer memory and FIFO host interface

Impact resistant circuit modules are disclosed for enclosing a die having a sensor area. Preferred modules include a flexible circuit and a die coupled thereto. The flexible circuit is preferably folded over compressible material to help absorb applied forces. A gap may be provided between sides of the die and the compressible material to help prevent peeling. A metal reinforcing layer may be bonded to the back of the die. A low modulus material including a patterned gap underneath the die may be used to absorb forces. A dry film adhesive may be placed between at least part of the upper surface of the die and the flexible circuit, preferably to provide further point impact resistance and protection. High and low modulus material may be combined in ruggedizing structures. Consumer devices employing such circuit modules are also taught, as well as module construction methods.

Circuit module having force resistant construction

A system and method for assembling dual-die integrated circuit packages using thermocompression bonding or thermosonic bonding to bond a second die to a substrate opposite a first die bonded to the substrate. The second die is bonded using heat conducted through the first die to the substrate, and optionally through an underfill material. The first and second die are connected such that bumps are connected to common bonding pads on the substrate. Bumps on one of the die extend through openings in the substrate to connect to the common bonding pads. The bonding pads are within the perimeter of the first die.

High density IC module

Turbulence inducers are provided on circuit modules. Rising above a substrate or heat spreader surface, turbulence generators may be added to existing modules or integrated into substrates or heat spreaders employed by circuit modules constructed according to traditional or new technologies.

Circuit module turbulence enhancement systems and methods

The present description provides increased contrast between interposer and leads in a stack embodiment that employs an interposer that extends beyond a boundary or perimeter established by the leads of the constituent IC devices.

Contrast interposer stacking system and method

The present invention provides a system and method for combining a leaded package IC and a semiconductor die using a flex circuitry to reduce footprint for the combination. A leaded IC package is disposed along the obverse side of a flex circuit. In a preferred embodiment, leads of the leaded IC package are configured to allow the lower surface of the body of the leaded IC package to contact the surface of the flex circuitry either directly or indirectly through an adhesive. A semiconductor die is connected to the reverse side of the flex circuit. In one embodiment, the semiconductor die is disposed on the reverse side of the flex while, in an alternative embodiment, the semiconductor die is disposed into a window in the flex circuit to rest directly or indirectly upon the body of the leaded IC package. Module contacts are provided in a variety of configurations. In a preferred embodiment, the leaded IC package is a flash memory and the semiconductor die is a controller.

Managed memory component

The present invention provides a system and method for devising stackable assemblies that may be then stacked to create a stacked circuit module. One or more integrated circuit (IC) die are disposed on one or more sides of a redistribution substrate that is preferably flexible circuitry. In some preferred embodiments, the die and redistribution substrate are bonded together and wire-bond connected. Two or more stackable assemblies are interconnected through frame members to create low profile high density stacked circuit modules.

Growing community of inventors

Austin, TX, United States of America

Leland Szewerenko