International Business Machines Corporation

Jds Uniphase Corporation

Leland Leslie Day

Paul Allen Ganfield

Steven Michael Douskey

Anthony Gus Aipperspach

Todd Alan Christensen

David Peter Gaio

William K Hogan

Charles Luther Johnson

Scott Michael Branch

Michael Francis Hanley

Michael Lynn Zumbrunnen

Guy Richard Currier

James Maurice Wallin

Paul W Wong

Murali Vaddigiri

The invention relates to an optical transceiver system for use in a host device including an optical transceiver receptacle or cage with a heat dissipating structure mounted thereon. The heat dissipating structure is electronically powered by an external source in the host device, which are electrically connected by insertion of a transceiver module into the transceiver receptacle. The present invention enables optical transceivers to support very high data rates, e.g. &#x3e;8 Gb/s, while still supporting very high density applications, e.g. SFF/SFP. Actuating features on the transceiver module and cage enable the heat dissipating structure to be turned on when the transceiver module is fully inserted into the cage, and turned off when the transceiver module is removed or at least partially removed from the cage.

Heat dissipating cages for optical transceiver systems

A push-to-release latching mechanism for retaining a transceiver module in a communication port of a computer or server is provided with a beam spring structure for positional restoration of the latch member, and the latch is supported and moveable relative to the host transceiver module. The latch member may be formed to include camming surfaces that facilitate the insertion of the transceiver module into a communication port and mate with a guide rail and connector resident in a communication port. The latch member may be adapted to latch with a rigid latch bar or a cantilevered spring. Additionally, the latch may be formed with a camming surface which insures that the latch is displaced to a latching position whenever network cables are connected to the transceiver module by camming the latch into the secure, latched position and subsequently preventing the latch from moving to an insecure or unlatched position. The latch member is pivotally supported on the transceiver module in a shaft/journal arrangement and thus is removed from the communication port whenever the transceiver module is removed, thereby preventing the latch from projecting from the communication port and being subject to damage. The latch member may be formed with a living hinge to provide a pivot axis and one end of the living hinge may be attached to a electronic module chassis or to a support structure which may be mated with a electronic module chassis for easy replaceability.

Pivoting type latch for removable electronic devices

A functional unit, such as an SRAM, in a single clock chip design that contains a scan path can be clocked on either rising edge and falling edge of the clock. The functional unit includes a clock signal having two phases and a plurality of latches for scanning. Two scan latches are added outside the array of the functional unit. In one clock phase, the two scan latches form a latch pair which is connected to the array at Scan-in side. In the other clock phase, one scan latch is connected to the array at the Scan-in side, and the other scan latch is connected to the array at the Scan-out side. In scan/hold operations, a first control signal for the array which is clocked at the falling edge of the clock leads a second control signal for the array which is clocked at the rising edge of the clock. In ABIST/functional operations, the first control signal for the array which is clocked at the falling edge of the clock trails the second control signal for the array which is clocked at the rising edge of the clock.

SRAM that can be clocked on either clock phase

A system and method for conducting a repeatable logic test on at least one functional unit of an IC chip includes steps of selecting at least one functional unit of at least several functional units, propagating test data through a part or all functional units of the time domain; and capturing test data of the selected functional unit. The functional units are either selected or held inactive such that only the selected functional unit is allowed to capture the test results for determining a critical timing path within the selected functional unit and only the functional unit. By selecting different combination of the functional unit(s), a number of the critical timing paths are readily determined in the chip.

System and method for using LBIST to find critical paths in functional logic

A data processing system, circuit arrangement, program product, and method thereof utilize a multi-path scan interface that is capable of providing multiple scan paths into a plurality of scan ring segments in an integrated circuit device. The multi-path scan interface utilizes one or more multiplexers coupled between scan in and scan out ports and at least one scan ring segment to provide alternate scan paths depending upon select signals supplied to each multiplexer. With such a configuration, a standardized scan interface may developed for interfacing with a wide variety of scan ring segments, and optionally, for multiple purposes. As a result, the amount of custom circuitry necessary to provide access to scan ring segments is significantly reduced.

Data processing system, circuit arrangement and program product

A method and apparatus for handling variable data word widths and array depths in an array built-in self-test system for testing a plurality of memory arrays using a single controller. Each array includes a predetermined row and column address depth and data word width. Each array further includes a scan register. A universal test data word is generated and sent to the scan register of each array. The universal length test data word has a length dependent upon the maximum row address depth, maximum column address depth and/or the maximum data word width. A portion of the test data word which exceeds the column address depth, row address depth and/or the data word width of a particular array is shifted off the end of the scan register of the particular array.

Method and apparatus for handling variable data word widths and array

A system and method for reducing simultaneous switching during scan-based testing of a system logic design. System logic is divided into clusters of system logic, and one or more scan chains are associated with each logic cluster. Each of the logic clusters are concurrently scan tested, yet circuitry in the scan chains associated with a cluster are triggered at different times than the circuitry in the scan chains of other clusters. Offset scan control signals provide the triggering for the scan chains of different clusters. Release and capture functions are also controlled to reduce simultaneous release and capture switching in different clusters.

Growing community of inventors

Rochester, MN, United States of America

Leland Leslie Day