Unisys Corporation

Leland E Watson

Bruce Ernest Whittaker

Saul Barajas

Scott Lane Brock

Stephanie Ninh Truong

An embodiment of the present invention is a technique for recording relevant information in a graphical user interface (GUI) window. Relevant information on an analysis window is saved in a summary report array using one of an automatic recording mode and a selective recording mode. The analysis window is part of the GUI to analyze state information from a panel dump file retrieved from a computer system. The saved relevant information is displayed on a report window.

Recording relevant information in a GUI window of a panel dump browser tool

An embodiment of the present invention is a technique to provide a graphical user interface (GUI) to analyze memory operations in a computer system. A job summary window shows state information of jobs in at least a unit panel. The unit panel represents at least a functional unit in the computer system. A memory job window shows state information of memory jobs in a functional unit selected from the unit panel to provide diagnostic information to the user. The state information being obtained from a panel dump file retrieved from the computer system.

Automatic analysis of memory operations using panel dump file

An embodiment of the present invention is a technique for providing a graphical user interface (GUI) to view system state of a computer system. An error window displays an error condition of a failed unit in a plurality of functional units in a computer system based on a panel dump file. A warning window shows a warning condition that potentially causes a problem in analyzing system state of the computer system or the error condition.

Displaying abnormal and error conditions in system state analysis

An enhanced computer system architecture provides a processor supported by a general cache and a mini-cache wherein the mini-cache will supply requested data words not available in the general cache thus eliminating the extra clock periods necessary to access main memory. The mini-cache stores frequently used data words and is refilled concurrently during processor command execution and is settable for handling data words or code words or both. A data queue storage stores a block of words which duplicate words in main memory. If the requested address matches an address register block in the mini-cache, the data queue store will make the words in the data queue available to requests from the processor. The mini-cache also monitors the system bus for any 'write' operations which might change the validity of the data in the address register block of the mini-cache. In this case, the data stored in the mini-cache is invalidated and cannot be used by the processor. Additionally, the mini-cache can be added to or removed from system operations.

Enhanced computer operational system using auxiliary mini-cache for

A mini-cache module is added to a computer system to increase throughput or may also be added to enhance the functionality of a general cache memory unit. The mini-cache module refills and stores frequently used data words concurrently during processor operations and provides them to the processor, eliminating the need to access a system bus to main memory. A data queue storage stores a data block of words from main memory and makes them available to requests from the main processor (if the requested address matches an address register block in the mini-cache). If an address 'hit' occurs, then the mini-cache will prevent any system bus request to main memory and additionally will monitor the system bus for any 'Write' operations which might feasibly change the validity of data in the data storage block of the mini-cache. In this case the data stored in the mini-cache is invalidated and cannot be used by the processor.

Mini cache operational module for enhancement to general cache

A message transfer system between multiple processors in a network. Each processor includes an interprocessor communications (IPC) hardware unit having an unique address count. An address count generator in a designated IPC hardware unit generates a sequence of binary count numbers such that when the generated count number matches the address of the IPC hardware unit, then that particular hardware unit and its associated processor are granted a time period of bus access for sending messages on the IPC network bus to other processors. Messages on the IPC network bus can be received by an IPC hardware unit at any time irrespective of the generated count number. Any sending processor that has bus access can concurrently provide multiple messages where each of the multiple messages is directed to each particular processor for reception. Thus one sender, with bus access, can communicate with multiple receivers during its transmission onto the IPC network bus connecting the processors.

Inter-processor communication net

In a digital data transfer system whereby a plurality of driver units are all connected to and share the same common system bus, there is provided control gating logic which will prevent the enablement of a subsequent driver for a fixed delay time until it is certain that the previous driver has been shut down. Due to switching time variations in driving units, a fixed delay time is set to function in a first driver that is beginning its data transmission to be sure that another driver which was previously transmitting data has been completely turned-off before the first driver gains access to the commonly shared bus. This ensures that no two drivers can simultaneously be driving data onto the system bus at the same time which would obviate the integrity of data transmitted.

Apparatus for preventing double drive occurrences on a common bus by

An automatic re-configurable computer system having a standard processor module and standard main memory and I/O control modules where each module is inter-connected to a common system bus. Automatic re-configuration occurs in the standard modules, when an optional module is connected onto the system bus, permitting inter-cooperation between the standard and optional modules to take place.

System for optional module detection and reconfiguration

Arbitration and control circuitry for monitoring the two processors sharing a system bus to insure fair access to system resources and to sense error conditions which occur in order to hold access for the processor involved until the error condition is cleared. The arbitration circuitry provides for two levels of bus access requests where one level involves normal requests and a second level involves priority request which take precedence over normal requests.

Multiprocessor multifunction arbitration system with two levels of bus

A programmable array logic unit (PAL) having a disconnected array of gates, inverters and D-Type flip-flops, is utilized by burning-in the interconnections, to enable the D flip-flops to function as J-K flip-flops and/or toggle flip-flops to enable flexibility in the functions available for utilization, by providing inputs for Direct Set, Direct Clear and Hold.

Flexible utilization of general flip-flops in programmable array logic

A system wherein multiple sources of data each have drivers for transmitting data to a common system bus. The drivers are each managed by individual enabling logic which is controlled by a flip-flop driven by a clock. Thus no driver can connect and drive data onto the bus until one clock period after the previously connected driver has been disabled and disconnected from the bus.

Growing community of inventors

Mission Viejo, CA, United States of America

Leland E Watson