International Business Machines Corporation

Leland D Howe, Jr

Bharatkumar Jayantilal Oza

Vincent A Scotto

Thomas J Roche

Frank Anthony Zurla, Jr

Glen LeRoy Hicks

Albert E Paniccia

An apparatus disposed within a computer system is disclosed for sensing the existence of an error occurring within a computer system and for suspending an internal system clock when a certain number of clock pulses are generated following the occurrence of the error. When the internal system clock is suspended, operation of the computer system stops. In the preferred embodiment, the internal system clock is suspended when two (2) clock pulses are generated following the occurrence of the error. As a result, it is not necessary to wait until execution of the current instruction is complete before stopping the operation of the computer system. Therefore, other errors are not generated within the computer system as a result of the generation of the initial error.

Apparatus for suspending a system clock when an initial error occurs

Clock generating apparatus for a computer system has selective pulse delay and pulse width control. Selection of pulse delay and pulse width is accomplished by loading registers with predetermined data patterns. The registers can be loaded under program control or by data entry units, such as a keyboard, switches, etc. The registers are located in coarse and fine pulse delay and pulse width adjustment units. These units have the same physical structure, but are functionally definable by a settable control element. A dither delay element is included in these coarse and fine adjustment units, and it is selectable to provide a small increment of delay. The coarse pulse delay and pulse width adjustment units also include pulse mode control circuitry to control operation in either normal oscillator mode or in single cycle mode.

Clock pulse generator with selective pulse delay and pulse width control

An instruction retry mechanism for enabling a digital data processing system having main, buffer and local stores to restart and, in most cases, recover from an error or failure in the processor hardware associated with the buffer and local stores. A first copy storage mechanism is provided for temporarily storing copies of data written into the local store. Two separately addressable multibit copy storage locations are provided for each local store address. One is capable of holding a copy of the latest data written into a given local store address during the most recent machine instruction cycle involving such address, and the other is capable of holding a copy of the latest data written into the same local store address during the next most recent machine instruction cycle involving such address. A second copy storage mechanism is provided for temporarily storing copies of data written into the buffer store by the instruction processing or instruction execution portion of the system. The storage capacity for this second copy mechanism is substantially smaller than the storage capacity of the buffer store. When the copy store becomes nearly full, room is made for new copies by causing the buffer store to copy back to the main store some of the modified data in the buffer store. This enables new buffer store data to be copied into the copy store in place of the data copied back to the main store without harm to the retry capability of the system. Three separately addressable multibit copy storage locations are provided for each buffer store address having a data copy in the copy store. One is capable of holding a copy of the latest data written into a given buffer store address during the most recent machine instruction cycle involving such address, and another is capable of holding a copy of the latest data written into the same buffer storage address during the next most recent machine instruction cycle involving such data. The third location is used to store a copy of the buffer store address and the main store address for the data Upon occurrence of a machine check interrupt or other error condition necessitating an instruction retry, all the copy data and address information in both copy storage mechanisms is transferred to a separate service processor which controls the retry operation. The service processor restores the data in the system to the condition which existed at the end of the machine instruction immediately preceding the instruction cycle during which the failure occurred. The service processor then instructs the system to repeat the instruction during which the failure occurred. Because two data copy locations are provided for each local store or buffer store address and because these two locations are used during different machine instruction cycles, one of them will, in most cases, include the proper copy for restoring the system to the condition existing at the start of the defective cycle.

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Owego, NY, United States of America

Leland D Howe, Jr