Inspur Electronic Information Industry Co., Ltd

Langchao Electronic Information Industry Co., Ltd.

Leijun Hu

Endong Wang

Rengang Li

Hongrui Han

Dong Zhang

Guangming Liu

Jicheng Chen

Weifeng Gong

Feng Zhang

Yong Dou

Xiangke Liao

Jun Luo

Hongwei Yin

Qingbo Wu

Yongwen Wang

Shouhao Wang

Jiaming Huang

Jizhi Zhao

Yi Zheng

An out-of-band updating method and system of an Expander, applied to a controller connected to the expander by means of a communication bus. The method comprises: receiving firmware updating data sent by a user (S); fragmenting the firmware updating data (S); and only when determining that the expander is in an idle state, sending the fragmented data until each piece of data is sent to the Expander, such that the expander completely receiving the firmware updating data completes updating by restarting (S). The data transmission speed is facilitated to be improved, the normal operation of a service is ensured, and the conditions of influencing state monitoring and log loss are avoided.

Out-of-band updating method and system of expander

A differential signal reversion and correction circuit and a method thereof are provided. The structures of the circuit include: a data frame sending module, when the link conditions are detected, the data frame sending module generates specific logic sequence and finishes the sending by a input/output port, such that a receiving side receives, processes and analyzes the sequence, and determination of link transmission conditions are achieved; a comparator of the receiving side, which receives sequence data, performs corresponding comparing, checking and feedback controlling, thereby achieving link detection and differential correction purpose; a reversion control signal generating module, which receives a comparison result of the comparator, generates corresponding control signal, and controls the link whether to perform reversion operation.

Differential signal reversion and correction circuit and method thereof

A method for building a multi-processor system with nodes having multiple cache coherency domains. In this system, a directory built in a node controller needs to include processor domain attribute information, and the information can be acquired by configuring cache coherency domain attributes of ports of the node controller connected to processors. In the disclosure herein, the node controller can support the multiple physical cache coherency domains in a node.

Method for building multi-processor system with nodes having multiple cache coherency domains

A design method of a repeater chip is provided, the repeater chip designed by using the method can implement interconnection among nodes, and implement packet sequence receiving, classifying, storing, forwarding, sorting, and transmitting functions of the repeater chip, thereby implementing effective extension of a high-speed transmission link among the nodes, so as to reduce hardware design difficulties and design risks. The structure of the repeater chip is formed by: an interface detecting unit, a sequence storing unit, a sequence forwarding unit, a sequence determining unit, and a sequence sorting unit.

Method of repeater chip

A close-coupling shared storage architecture of double-wing expandable multiprocessor is provided in the close-coupling shared storage architecture with p processors scale, the close-coupling shared storage architecture of double-wing expandable multiprocessor comprises: j processor modules PMs; wherein, each processor module is formed by coupling and cross-jointing i processors Cs, and each processor is directly connected with a node controller NC through only one link; each processor module PM comprises 2 pairing node controllers NCs, and each node controller NC is connected with the processors through m links and is connected with an interconnect network through n links; the interconnect network comprises two groups, and each group comprises k cross switch route chips NRs, each of which has q ports. By adopting the connection method above, the close-coupling shared storage architecture of double-wing expandable multiprocessor is formed. On the premise that the processor scale is kept expandable, the balance between the processor bandwidth and the network bandwidth is achieved, and the lower average delay of the interconnect network is kept simultaneously.

Close-coupling shared storage architecture of double-wing expandable multiprocessor

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Jinan, China

Leijun Hu