Intel Corporation

Leigh M Tribolet

Robert L Sankman

Debendra Mallik

Ravindranath Vithal Mahajan

Sanka Ganesan

Kevin T McCarthy

Pramod Malatkar

Kyle Yazzie

Patrick Nardi

Kevin Y Lin

Venkata Suresh R Guthikonda

Santosh Sankarasubramanian

John L Harper

Embodiments include semiconductor packages and methods to form the semiconductor packages. A semiconductor package includes a bridge over a glass patch. The bridge is coupled to the glass patch with an adhesive layer. The semiconductor package also includes a high-density packaging (HDP) substrate over the bridge and the glass patch. The HDP substrate is conductively coupled to the glass patch with a plurality of through mold vias (TMVs). The semiconductor package further includes a plurality of dies over the HDP substrate, and a first encapsulation layer over the TMVs, the bridge, the adhesive layer, and the glass patch. The HDP substrate includes a plurality of conductive interconnects that conductively couple the dies to the bridge and glass patch. The bridge may be an embedded multi-die interconnect bridge (EMIB), where the EMIB is communicatively coupled to the dies, and the glass patch includes a plurality of through glass vias (TGVs).

Multi-die ultrafine pitch patch architecture of interconnect bridge over glass layer and method of making

Embodiments include semiconductor packages and methods to form the semiconductor packages. A semiconductor package includes a bridge with a hybrid layer on a high-density packaging (HDP) substrate, a plurality of dies over the bridge and the HDP substrate, and a plurality of through mold vias (TMVs) on the HDP substrate. The bridge is coupled between the dies and the HDP substrate. The bridge is directly coupled to two dies of the dies with the hybrid layer, where a top surface of the hybrid layer of the bridge is directly on bottom surfaces of the dies, and where a bottom surface of the bridge is directly on a top surface of the HDP substrate. The TMVs couple the HDP substrate to the dies, and have a thickness that is substantially equal to a thickness of the bridge. The hybrid layer includes conductive pads, surface finish, and/or dielectric.

Ultrathin bridge and multi-die ultrafine pitch patch architecture and method of making

Multi-die ultrafine pitch patch architecture and method of making

An apparatus, comprising a first platform comprising a first working surface having a first non-planar portion; and a second platform comprising a second working surface having a second non-planar portion, wherein: the second working surface is opposite the first working surface, a distance between the first working surface and the second working surface is adjustable, the first non-planar portion comprises a first curved portion, and the second non-planar portion comprises a second curved portion opposite the first curved portion.

Constrained cure component attach process for improved IC package warpage control

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Chandler, AZ, United States of America

Leigh M Tribolet