Texas Instruments Corporation

Texas Instruments Incorporated Deutschland, Gmbh

Leif Christian Olsen

Leland Scott Swanson

James Joseph Chambers

Manuel A Quevedo-Lopez

Christoph Andreas Othmar Dirnecker

Henry Litzmann Edwards

Howard L Tigelaar

Robert G Fleck

The invention relates to a semiconductor device and a method of manufacturing an electronic device. A first conductive layer (first metal interconnect layer) is deposited. There is an insulating layer (first intermetal dielectric) layer deposited. A resistive layer is deposited on top of the insulating layer and structured in order to serve as a thin film resistor. A second insulating layer (second intermetal dielectric) is then deposited on top of the resistive layer. A first opening is etched into the insulating layers (first and second intermetal dielectric) down to the first conductive layer. A second opening is etched into the insulating layers (first and second intermetal dielectrics) down to the first conductive layer. A cross-sectional plane of the second opening is arranged such that it at least partially overlaps the resistive layer of the thin film resistor in a first direction.

Semiconductor device and method for low resistive thin film resistor interconnect

Areas of a semiconductor substrate where semiconductor devices are not to be formed are filled in with dummy active areas. Whole dummy active areas are formed in areas of the semiconductor substrate where semiconductor devices are not to be formed, and partial dummy active areas are formed in areas of the semiconductor substrate where semiconductor devices are not to be formed, but where whole dummy active areas can not be accommodated. The dummy active areas are staggered so as to provide uniform parasitic capacitive coupling to overlying leads regardless of the placement of the leads. The dummy active areas are substantially evenly separated from one another by dividers. The dummy active areas and dividers are formed concurrently with formation of semiconductor devices in non-dummy active areas. The dummy active areas mitigate yield loss by, among other things, providing more uniformity across the substrate, at least with regard to parasitic capacitances and stress and subsequent processing.

Dummy active area implementation

The present invention facilitates semiconductor fabrication by maintaining shape and density of an etch stop layer () during trench fill operations. The shape and density of the etch stop layer () is maintained by forming a protective alloy liner layer () on the etch stop layer () prior to trench fill operations. The protective alloy liner () is comprised of an alloy that is resistant to materials employed in the trench fill operations. As a result, clipping and/or damage to the etch stop layer () is mitigated thereby facilitating a subsequent planarization process that employs the etch stop layer (). Additionally, selection of thickness and composition () of the formed protective alloy () yields a stress amount and type () that is applied to channel regions of unformed transistor devices, ultimately providing for an improvement in channel mobility.

Methods and systems to mitigate etch stop clipping for shallow trench isolation fabrication

Silicon carbide is used for a hardmask for the isolation dielectric etch and also serves as an etch stop for chemical-mechanical polishing. Alternatively, silicon carbonitride or silicon carboxide can be used.

Silicon carbide as a stop layer in chemical mechanical polishing for isolation dielectric

An inlaid interconnect fabrication method using a silicon carbide polish stop layer for protection of mechanically weak dielectric such as porous silicon dioxide (xerogel) during chemical mechanical polishing.

Integrated circuit interconnect and method

Silicon carbide (SiC) is used as the stop layer for the chemical-mechanical polishing used to planarize the surface of interlevel dielectrics, making the resistance of the vias more uniform. Alternatively, silicon carbonitride or silicon carboxide can be used in place of silicon carbide.

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Plano, TX, United States of America

Leif Christian Olsen