Cirrus Logic Inc.

University of Texas System

New York University

Florida State University Research Foundation, Inc.

Cirrus Logic International Semiconductor Limited

Lei Zhu

Xiaofan Fei

Xin Zhao

John L Melanson

Tejasvi Das

Johann Guy Gaboriau

Ku He

Wai-Shun Shum

Alan Mark Morton

Jing Bai

Leyi Yin

Amar Vellanki

Saurabh Singh

Yongjie Cheng

Eric V Anslyn

Vamsikrishna Parupalli

Nadrian C Seeman

Bhoodev Kumar

James Wayne Canary

Kyehyung Lee

Graeme Gordon Mackay

Miao Song

Philip Lukeman

Eric Jerome King

Christian Larsen

Lingli Zhang

Thomas H Hoff

Zhao Yuan

Nishant Jain

Vinod Jayakumar

Wei-Shun Shum

Hossein Mirzaie

Gui-Chao Kuang

Jan Frantz Folmer-Andersen

J Frantz Folmer-Andersen

Johann G Gaboriau

A single integrated circuit may include a signal path configured to generate an output signal from an input signal, wherein the signal path includes an amplifier configured to drive the output signal, a direct-current-to-direct-current (DC-DC) power converter having a power inductor integrated in the single integrated circuit and configured to generate a supply voltage to the amplifier from a source voltage to the DC-DC power converter, and control circuitry for controlling operation of converter switches of the DC-DC power converter in order that the supply voltage tracks at least one among the input signal and the output signal.

On-chip inductor with audio headphone amplifier

A differential output current digital-to-analog converter (IDAC) circuit may include a delta-sigma modulator configured to receive a digital input signal, a control circuit responsive to the delta-sigma modulator configured to perform a DAC decode operation, a plurality of DAC elements responsive to the DAC decode operation, the plurality of DAC elements configured to, in concert, generate a differential output current signal based on the digital input signal to a load coupled to a pair of output terminals of the IDAC, and an output impedance coupled between the pair of output terminals such that the output impedance is in parallel with the load.

Current digital-to-analog converter with high-impedance output

A driver system may include a first n-type field-effect transistor coupled at its non-gate terminals between an output of the driver system and a first terminal of a supply voltage and configured to drive the output when the first n-type field-effect transistor is activated, a second n-type field-effect transistor coupled at its non-gate terminals between an output of the driver system and a second terminal of the supply voltage and configured to drive the output when the second n-type field-effect transistor is activated, a high-side capacitor coupled to the output of the driver system, and a low-side capacitor coupled to the second terminal of the supply voltage, wherein the high-side capacitor and the low-side capacitor are configured to track and correct for mismatches between a first resistance of the first n-type field-effect transistor and a second resistance of the second n-type field-effect transistor.

Dual bootstrapping for an open-loop pulse width modulation driver

A system may include a current digital-to-analog converter (IDAC) configured to convert a digital input signal into an output current signal and a switched-mode power supply configured to provide electrical energy in the form of a supply voltage to the IDAC for operation of the IDAC, the switched-mode power supply configured to track a voltage signal derived from the digital input current signal and generate the supply voltage based on the voltage signal and a voltage headroom above the voltage signal.

Using a tracking switched-mode power supply to increase efficiency of a current digital-to-analog converter-based output stage

A differential output current digital-to-analog (IDAC) circuit may include a delta-sigma modulator configured to receive a digital input signal, a control circuit responsive to the delta-sigma modulator configured to perform a DAC decode operation, a plurality of DAC elements responsive to the DAC decode operation, the plurality of DAC elements configured to, in concert, generate a differential output current signal based on the digital input signal to a load coupled to a pair of output terminals of the IDAC, and a plurality of warming switches, each warming switch coupled to a respective bias transistor of a respective DAC element of the plurality of DAC elements, wherein the control circuit may further be configured to selectively control each such warming switch in order to selectively de-bias and bias a respective bias transistor of such warming switch when a respective DAC element of the respective bias transistor is output-disabled from generating the differential output current signal.

Current digital-to-analog converter with warming of digital-to-analog converter elements

In accordance with embodiments of the present disclosure, a system may include a buffer and a switch coupled between the buffer and a voltage supply such that the switch controls a varying voltage at a varying voltage node coupled to the buffer.

Control of switches in a variable impedance element

In accordance with embodiments of the present disclosure, a method for power supply rejection for an amplifier may include generating a correction signal by multiplying a quantity indicative of a power supply voltage of the amplifier by a transfer function defining a response from the power supply voltage of the amplifier to an output signal of the amplifier and subtracting the correction signal from a signal within a signal path of a circuit comprising the amplifier.

Amplifier offset cancellation using amplifier supply voltage

A system may include a digital modulator configured to modulate an input signal received at an input of the digital modulator to generate a modulated input signal at an output of the digital modulator, a digital gain element having a digital gain and coupled to the digital modulator, an open-loop Class-D amplifier coupled to an output of the digital modulator and configured to amplify the modulated input signal, wherein the open-loop Class-D amplifier is powered from a variable power supply having a variable supply voltage which is variable in response to one or more characteristics of the input signal, and a control circuit configured to control the digital gain to approximately cancel changes in an analog gain of the open-loop Class-D amplifier due to variation in the variable supply voltage in response to the one or more characteristics of the input signal.

Gain control in a class-D open-loop amplifier

A digital delta-sigma modulator may include a loop filter having a loop filter input configured to receive an input signal and generate an intermediate signal responsive to the input signal and a multi-bit quantizer configured to quantize the intermediate signal into a quantized output signal which is fed back as an input to the loop filter. The multi-bit quantizer may further be configured to operate in at least two modes comprising: (a) a normal mode in which, for each sample of the intermediate signal, the multi-bit quantizer generates a corresponding sample having a value selected from a set of a plurality of quantization levels; and (b) a code suppression mode in which, for each sample of the intermediate signal, the multi-bit quantizer generates a corresponding sample having a value selected from a subset of the set of a plurality of quantization levels.

Increased noise performance using quantizer code suppression

A system may include a filter configured to receive a digital audio input signal quantized at between two and 257 quantization levels and sampled at at least 500 kilohertz, the filter further configured to perform filtering on the digital audio input signal to generate a filtered digital audio input signal, the filter having a selectable variable group delay, a digital-to-analog converter configured to receive the filtered digital audio input signal and convert the filtered digital audio input signal into an equivalent analog audio input signal, and a driver configured to receive the equivalent analog audio input signal and drive an analog audio output signal to a transducer.

Low-latency audio output with variable group delay

An apparatus detects a short of a class-D amplifier. A pulse detector detects an output PWM pulse exceeds a predetermined width and a controller differentiates whether the pulse width exceeding is caused by a short or by a large digital input signal occurring during normal operation based on an expected level of the digital input signal to a level of the digital input signal when the pulse width exceeds the predetermined width. The expected level is dynamically obtained in response to one or more previous PWM pulses exceeding the predetermined width during the normal operation and may be selected based on an amount the pulse exceeds the predetermined width. A lookup table of predetermined levels, selected based on impedance of a load, provides the expected level if the expected level has not yet been dynamically obtained when the pulse width exceeds.

Digital short detection method of class D amplifier

A signal processing system may include a modulation stage configured to generate a modulated input signal, an open-loop switched mode driver coupled to the modulation stage and configured to generate an output signal from the modulated input signal, a voltage regulator configured to generate a supply voltage that supplies electrical energy to the open-loop switched mode driver, and a control subsystem configured to, when a magnitude of the modulated input signal falls below a threshold magnitude, control the voltage regulator to control the supply voltage such that the output signal varies non-linearly with the modulated input signal for magnitudes of the modulated input signal below the threshold magnitude.

Open-loop class-D amplifier system with analog supply ramping

Resistor mismatch may be digitally compensated based on a known resistor mismatch, power supply information, and/or other operating parameters of the amplifier. The digital compensation may be applied to the digital input signal before conversion for processing and amplification in the analog domain. An amplifier with digital compensation for resistor mismatch may be used in a class-D amplifier with a closed loop and feedforward feedback. A class-D or other amplifier with digital compensation may be integrated with electronic devices such as mobile phones.

Closed-loop digital compensation scheme

In a signal path comprising an analog path portion configured to operate in a plurality of output impedance modes including a high impedance mode with a first impedance and a low impedance mode with a second impedance, and a digital path portion having a variable digital gain and configured to convert a digital input signal and into an analog signal provided to the analog path portion, a method may include responsive to a condition for switching between the high impedance mode and the low impedance mode or vice versa, transitioning the output impedance continuously or in a series of steps between the first impedance and the second impedance or vice versa and, contemporaneously with transitioning the output impedance, transitioning the variable digital gain continuously or in a series of steps such to maintain a substantially constant overall path gain for the signal path remains substantially constant during transition.

Growing community of inventors

Austin, TX, United States of America

Lei Zhu