China Electronic Technology Corporation, 24th Research Institute

University of California

No. 24 Research Institute of China Electronic Technology Corporation

No. 26 Research Institute of China Electronics Technology Group Corporation

Zein Biotechnology Co., Ltd.

Lei Zhang

Can Zhu

Rong-Ke Ye

Guang-Bing Chen

Gang-Yi Hu

Yu-Han Gao

Zheng-Ping Zhang

Rong-Bin Hu

Yong-Lu Wang

Min Zhao

Junfeng Feng

Dongbing Fu

Guangbing Chen

Yuxin Wang

Yan Wang

Liang Li

Zhengping Zhang

Dong-Bing Fu

Yu-Xin Wang

Xi Chen

Rongbin Hu

Xi Wang

Huaiqiang Yu

Yonglu Wang

Shan Huang

Yuhan Gao

Xing-Fa Huang

Xu Huang

Jiao-Xue Li

He-Quan Jiang

Bin Cheng

Chuangxin Jiang

Mingyan Jiang

Like Deng

Meirui Liu

Shiyi Jiang

Xiao Peng

Jinyi Ma

Tianshuai Xu

Zhichuan Huang

Junwei Shen

Dayong Gong

Xin Gao

Yumei Xiao

Gnag-Yi Hu

Zhanghong Wang

Rongke Ye

Xue-Liang Xu

Xiao-Feng Shen

Ming-Yuan Xu

You-Hua Wang

Provided is a method for biosynthesis of (R)-β-hydroxytetradecanoate compounds. The method comprises the following steps of: reacting β-carbonyl tetradecanoate in a ketoreductase and a glucose dehydrogenase or a fusion enzyme thereof, glucose, NADPand a buffer solution to obtain (R)-β-hydroxytetradecanoate compounds. The method is an enzyme-catalyzed biosynthesis method having simple operations, conventional equipment and an environmentally friendly process, and the prepared product has high purity, high yield and a high ee value.

Use of biological enzyme for preparing orlistat intermediate, and preparation method

The disclosure provides a method for assembling and interconnecting FBAR filter and an electronic device. The method includes constructing an equivalent circuit model of an assembled FBAR filter according to a circuit model of a filter chip and the grounding circuit of the FBAR filter; modeling, simulating and calculating the grounding circuit to extract parasitic parameters corresponding to the grounding pad and a grounding bond-wire of the grounding circuit, respectively; feedbacking the parasitic parameters back into the equivalent circuit model, and using the circuit simulation software to obtain an S parameter of the filter; adjusting the parasitic parameters of the grounding circuit to optimize an S parameter performance of the FBAR filter: obtaining an optimal assembly configuration of the FBAR filter to guide the assembly. The parasitic parameters include a parasitic inductance of the grounding bond-wire and a parasitic capacitance and parasitic inductance of the grounding pad.

Film bulk acoustic resonator filter assembling and interconnecting method and electronic device

A comparator offset voltage self-correction circuit is disclosed. A comparator offset voltage which is caused by the semiconductor process parameter randomness also has randomness. Due to the randomness of the comparator offset voltage, a reference voltage of a parallel comparator in a parallel-conversion-type analog-to-digital converter is uncertain. If the comparator offset voltage is large, the parallel-conversion-type analog-to-digital converter may even have a functional error. The comparator offset voltage self-correction circuit provided in the present invention can correct a random offset voltage of a comparator to meet requirements. Therefore, by means of the circuit and a method provided in the present invention, adverse influence of the random offset of the comparator on the function and the performance of the parallel-conversion-type analog-to-digital converter is eliminated, thereby greatly improving the speed and the performance of the analog-to-digital converter, in particular the parallel-conversion-type analog-to-digital converter.

Comparator offset voltage self-correction circuit

The invention provides a clock delay adjusting circuit based on edge addition and an integrated chip thereof. The clock delay adjusting circuit comprises a clock delay unit, a weight coefficient unit and an edge addition unit, wherein the clock delay unit is used for conducting equal-interval delay on clock signals inputted into the input end of the clock delay unit to obtain and output at least three delay clock signals at equal intervals, the weight coefficient unit is used for generating weight signals with the number the same as the number of the delay clock signals according to digital codes inputted into the input end of the weight coefficient unit and outputting the weight signals, and the edge addition unit is used for receiving the delay clock signals and the weight signals, conducting weighted summation on the delay clock signals according to the weight signals and outputting signals obtained through weighted summation to obtain new clock signals with continuous clock rising edges/continuous clock falling edges, wherein the number of the new clock signals is the same as the number of the delay clock signals. In addition, the clock delay adjusting circuit can be made into the integrated chip. In view of the present invention, the problems that an existing clock delay adjusting circuit is low in adjustment accuracy and can not meet the requirement for high-precision time-share sampling are well solved.

Clock delay adjusting circuit based on edge addition and integrated chip thereof

A track and hold circuit comprises an input buffer amplifier, a unit gain amplifier module, a sampling switch, a drive triode and a sampling capacitor. The input buffer amplifier receives an input signal. In a track phase, the sampling switch is electrically connected to an emitter electrode of the drive triode; the input signal charges the sampling capacitor after being buffered by the input buffer amplifier, amplified without distortion by the unit gain amplifier module and driven by the drive triode. In a hold phase, the sampling switch is electrically connected to a base electrode of the drive triode; the base voltage of the drive triode is pulled down until the drive triode is cut off; electrical charges on the sampling capacitor are thereby held, causing the signal to be held on the sampling capacitor.

Track and hold circuit

Systems and methods are provided for migrating cells implanted or endogenous in tissue. The system may include first and second delivery electrodes configured for insertion in tissue and a direct current (DC) power source operatively coupled to the first and second delivery electrodes. The system further may include a programmable controller operatively coupled to the DC power source, wherein the programmable controller is programmed to direct the DC power source to deliver an electric field between the first delivery electrode and the second delivery electrode at a stimulation to nonstimulation ratio sufficient to cause the cells to migrate within tissue selectively.

Systems and methods for selectively migrating cells using electric fields

A band-gap reference circuit includes a proportioned current generating circuit, a startup circuit, a current mirror circuit, a high-order temperature compensation generating circuit and a reference generating circuit. The proportioned current generating circuit is configured to generate a current in direct proportion to the absolute temperature. The startup circuit is configured to start up the proportioned current generating circuit when the startup circuit is power on. The current mirror circuit is configured to reproduce a current which is the same as the current in direct proportion to the absolute temperature. The high-order temperature compensation generating circuit is configured to generate a compensation current of high-order temperature coefficient. The reference generating circuit is configured to add the voltage which is generated by the proportioned current generating circuit to a voltage of negative temperature coefficient according to a certain proportion, and output a reference voltage of zero temperature coefficient.

Band-gap reference circuit based on temperature compensation

A high-linearity CMOS input buffer circuit is provided for neutralizing non-linearity of follower circuits' transconductance and output impedance resulting from input signals' variation. In doing so, the linearity of CMOS input buffer is improved. The buffer circuit includes a CMOS input follower circuit, a linearity improvement circuit of follower transistor, a current source load, and a linearity improvement circuit of load impedance. The buffer circuit is fabricated in standard CMOS process, featuring low cost, simplicity and strong linearity at high frequency. It has wide applications in analog and hybrid analog-digital CMOS ICs requiring high linearity input buffer.

CMOS input buffer circuit

Growing community of inventors

Chongqing, China

Lei Zhang