Innoscience (suzhou) Semiconductor Co., Ltd.

Freescale Semiconductor,inc.

Soochow University

Nxp Usa, Inc.

Innoscience (suzhou) Technology Co., Ltd.

Suzhou Venmed Technology Co., Ltd.

Deartech Machine Tool (suzhou) Corp., Ltd.

Lei Zhang

Kai Cao

Chunhua Zhou

King Yuen Wong

Xiaoxiang Geng

Weigang Yao

Shayan Zhang

Jun Wang

Qian Wang

Cheng Fan

Kejun Wang

Xuewen He

Jianping Zhang

Yonggang Wang

Yin Guo

Kun Wu

Xiaotian Wang

Haiquan Feng

Lei Gao

Jing Li

Shangqing Qiu

Yifeng Zhu

Zezhong Lu

Lijuan Guan

Yucheng Xue

Haifeng Bai

Lixin Wang

Zhenguang Li

The invention discloses a microcrack-based strain sensing element and a preparation method and use thereof. The microcrack-based strain sensing element includes a substrate layer, a metal film, a protective layer, an output electrode, and a packaging layer. The metal film is arranged on the substrate layer. The metal film is formed by deposition of two metal materials. The metal film is provided with a patterned crack structure. The protective layer is arranged on the metal film. The output electrode is connected to the metal film for outputting an electrical signal. The packaging layer is arranged on the protective layer. Compared with existing crack preparation technologies, the preparation method of the microcrack-based strain sensing element of the invention has higher-precision crack controllability, does not affect the service life of cracks, and achieves more optimized actual operation. The microcrack-based strain sensing element has the advantages of high sensitivity, wearable performance and miniaturization.

Microcrack-based strain sensing element, preparation method and use thereof

A thrombus treatment platform comprises an aspiration catheter, an aspiration pump, a stirring device and a filter assembly, the filter assembly comprises a filter rod and a filter screen; the stirring device comprises a first catheter, a second catheter, a stirrer and an operating device capable of causing the first catheter and the second catheter to slide relatively so that the stirrer can be switched between the expanded state and the collapsed state; the thrombus treatment platform further comprises a driving device capable of driving the rotation of the stirrer. The present disclosure can remove thrombus under the condition of ensuring relative safety, and is particularly suitable for removing a large number of thrombus in the inferior vena cava, protects venous valves and venous vessel walls, has controllable blood loss and simple operation steps, shortens operation time, and reduces patient hospitalization expenses.

Thrombus treatment platform

A III-nitride-based semiconductor packaged structure includes a lead frame, an adhesive layer, a III-nitride-based die, an encapsulant, and at least one bonding wire. The lead frame includes a die paddle and a lead. The die paddle has first and second recesses arranged in a top surface of the die paddle. The first recesses are located adjacent to a relatively central region of the top surface. The second recesses are located adjacent to a relatively peripheral region of the top surface. The first recess has a shape different from the second recess from a top-view perspective. The adhesive layer is disposed on the die paddle to fill into the first recesses. The III-nitride-based die is disposed on the adhesive layer. The encapsulant encapsulates the lead frame and the III-nitride-based die. The second recesses are filled with the encapsulant. The bonding wire is encapsulated by the encapsulant.

III-nitride-based semiconductor packaged structure and method for manufacturing the same

A nitride semiconductor device includes a semiconductor carrier, a first nitride-based chip, and first conformal connecting structures. The first nitride-based chip is disposed over the semiconductor carrier. The semiconductor carrier has a first planar surface. The first nitride-based chip has a second planar surface, first conductive pads, and first slanted surfaces. The first conductive pads are disposed in the second planar surface. The first slanted surfaces connect the second planar surface to the first planar surface. The first conformal connecting structures are disposed on the first planar surface and the first nitride-based chip. First obtuse angles are formed between the second planar surface and the first slanted surfaces. Each of the first conformal connecting structures covers one of the first slanted surfaces of the first nitride-based chip and one of the first obtuse angles and is electrically connected to the first conductive pads.

Nitride semiconductor device and method for manufacturing the same

Disclosed is a device for polishing an intraocular lens by using an electrorheological effect. The device comprises a supporting plate (), an electric motor (), a conductive slip ring (), an outer sleeve (), a tool shaft (), a connecting flange (), an annular electrode () and a tool needle (). The electric motor (), an outer ring of the conductive slip ring (), and the outer sleeve () are all installed on the supporting plate (). The electric motor () drives the tool shaft () to rotate by means of a transmission assembly. One end of the tool shaft () is closely fitted with an inner ring of the conductive slip ring (), and the other end of the tool shaft extends into the outer sleeve (). The connecting flange () is installed on the outer sleeve (). The annular electrode () is connected to the connecting flange (). One end of the tool needle () is connected to the tool shaft (), and the other end of the tool needle extends out of the annular electrode (). The tool needle is used as a cathode and the annular electrode is used as an anode in the apparatus. The apparatus thus has a good insulation effect and both tool needle and annular electrode can be detached and adjusted, such that different polishing requirements can be met, and high-quality deterministic polishing for an aspherical intraocular lens can be completed. Further the present invention provides a method for polishing an intraocular lens by using an electrorheological effect.

Apparatus and method for polishing intraocular lens by utilizing electrorheological effect

An integrated semiconductor device includes a substrate, semiconductor circuit layers, a first insulating layer, a second insulating layer, and an interconnection layer. The semiconductor circuit layers are disposed above the substrate. The semiconductor circuit layers have device portions and isolating portions, and the isolating portions are located among the device portions. The first insulating layer is disposed on the semiconductor circuit layers, and the second insulating layer is disposed on the first insulating layer, and the interconnection layer is disposed on the semiconductor circuit layers. The interconnection layer penetrates the first and second insulating layers to electrically connect the device portions of the semiconductor circuit layers. The second insulating layer or the first and second insulating layers collectively form one or more isolating structures above the isolating portion of the semiconductor circuit layers. The interconnection layer has a plurality of first circuits located above the device portions.

Integrated semiconductor device and method for manufacturing the same

An integrated semiconductor device includes a substrate, semiconductor circuit layers, an insulating material, and an interconnection layer. The semiconductor circuit layers are disposed above the substrate. The semiconductor circuit layers have device portions and isolating portions, and the isolating portions are located among the device portions. The insulating material is disposed on the semiconductor circuit layers, and the interconnection layer is embedded in the insulating material and electrically connected to the semiconductor circuit layers. The isolating portions provide electrical isolation between adjacent device portions. The interconnection layer has circuits embedded in the insulating material on the device portions. The insulating material has isolating structures raised from top surfaces of the circuits on the device portion, and some of the semiconductor circuit layers form at least one heterojunction.

An integrated circuit includes on-chip flash memory, a EEPROM, cache memory, and a repair controller. When a defective address is detected in the flash memory, data slotted to be stored at the defective address is stored in the EEPROM by the repair controller. The cache memory includes a content addressable memory (CAM) that checks read addresses with the defective memory address and if there is a match, the data stored in the EEPROM is moved to the cache so that it can be output in place of data stored at the defective location of the flash memory. The memory repair system does not require any fuses nor is the flash required to include redundant rows or columns. Further, defective addresses can be detected and repaired on-the-fly.

Non-volatile memory repair circuit

A power management circuit for integrated circuits operating systems where the power supply may be marginal includes a supply voltage characterization circuit and a clock synthesis circuit. The supply voltage characterization circuit determines the strength of the supply voltage applied to the IC and provides information to the synthesis circuit that is used to adjust the clock frequency of the IC to insure the IC does not draw too much current and force the IC into reset. A counter is used to determine the time between when the supply voltage reaches a first level and a second higher level, the time being representative of the slope of the supply voltage. Knowledge of the characteristics of a portion of the circuit under certain operating or benchmark conditions may be used to adjust the characterization.

Power management system for integrated circuits

A system for prototyping an integrated circuit (IC) that has a mixed signal intellectual property (IP) core includes implementing the IP core using discrete programmable digital ICs and discrete analog ICs by partitioning the IP core into a digital IP portion and an analog IP portion.

Mixed signal IP core prototyping system

Growing community of inventors

Suzhou, China

Lei Zhang