Globalfoundries Inc.

Apple Inc.

Lei Yuan

Jongwook Kye

Harry Jay Levinson

Mahbub Rashed

Juhan Kim

Jia Zeng

Jason Eugene Stephens

Youngtag Woo

Soo Han Choi

Yan E Wang

Li Ping Yang

Hidekazu Yoshida

Guillaume Bouche

Jin Haeng Cho

Tuhin Guha Neogi

Chenchen Wang

Irene Yuh-Ling Lin

Wenhui Wang

Sudharshanan Raghunathan

Jung Yen Huang

Doh-Hyoung Lee

Niva A Ran

Jiun-Jye Chang

Po-Chun Yeh

Ching-Sang Chuang

Chuan-Jung Lin

Themistoklis Afentakis

Andy Chi-Hung Wei

Caleb Coburn

Shih Chang Chang

Qi Xiang

Cheng Kai Chen

Rui Liu

Ting-Kuo Chang

Chun-Yao Huang

Suresh Venkatesan

Chieh-Wei Chen

Shinya Ono

Sunggu Kang

Jungmin Lee

Enkhamgalan Dorjgotov

Srinivasa Banna

Graham Butler Myhre

David C Pritchard

Andrew C Lin

James E Pedder

Steven E Molesa

Ivan Knez

Yunfei Deng

Chia-Yu Chen

Giovanni Carbone

Xuelian Zhu

Cheuk Chi Lo

Chun-Ming Tang

Michael Slootsky

Jaein Choi

Irene Y Lin

Wendi Chang

Gloria Wong

Lixia Lei

Hairong Tang

Hitoshi Yamamoto

Kwang Ohk Cheon

KiBeom Kim

Gwanwoo Park

Paul D Mesa

Qinglei Wang

Andrew H Lin

Chih-Hung Yu

Xingfeng He

Yung Fong Kao

Shih Lun Huang

Irene Y L Lin

EnkhAmgalan Dorjgotov

Cheng Chen

Rni Liu

An organic light-emitting diode (OLED) display may have an array of organic light-emitting diode pixels that each have OLED layers interposed between a cathode and an anode. Voltage may be applied to the anode of each pixel to control the magnitude of emitted light. The conductivity of the OLED layers may allow leakage current to pass between neighboring anodes in the display. To reduce leakage current and the accompanying cross-talk, the display may include active and/or passive leakage-mitigating structures. The passive leakage-mitigating structures may have an undercut that causes discontinuities in the overlying OLED layers. Active leakage-mitigating structures may include a conductive layer (e.g., a conductive ring) that drains leakage current to ground. Alternatively, the active leakage-mitigating structures may include a gate electrode modulator with a variable voltage that stops the current flow laterally.

Organic light-emitting diode display with passive leakage-reducing structures

Organic light-emitting diode display with active leakage-reducing structures

An organic light-emitting diode (OLED) display may have an array of organic light-emitting diode pixels that each have OLED layers interposed between a cathode and an anode. Voltage may be applied to the anode of each pixel to control the magnitude of emitted light. The conductivity of the OLED layers may allow leakage current to pass between neighboring anodes in the display. To reduce leakage current and the accompanying cross-talk in a display, the pixel definition layer may disrupt continuity of the OLED layers. The pixel definition layer may have a steep sidewall, a sidewall with an undercut, or a sidewall surface with a plurality of curves to disrupt continuity of the OLED layers. A control gate that is coupled to a bias voltage and covered by gate dielectric may be used to form an organic thin-film transistor that shuts the leakage current channel between adjacent anodes on the display.

Organic light-emitting diode display with reduced lateral leakage

At least one method, apparatus and system disclosed involves a circuit layout for an integrated circuit device comprising a plurality of wider-than-default metal formations for a functional cell. A design for an integrated circuit device is received. The design comprises at least one functional cell. A first pair of wide metal formations are provided. The first pair of wide metal formations comprise a first metal formation and a second metal placed about a first cell boundary of the functional cell for providing additional space for routing, for high-drive routing, and/or for power routing.

Method, apparatus and system for wide metal line for SADP routing

At least one method, apparatus and system disclosed herein for forming a finFET device having a pass-through structure. A first gate structure and a second gate structure are formed on a semiconductor wafer. A first active area is formed on one end of the first and second gate structures. A second active area is formed on the other end of the first and second gate structures. A trench silicide (TS) structure self-aligned to the first and second gate structures is formed. The TS structure is configured to operatively couple the first active area to the second active area.

Methods, apparatus and system for a passthrough-based architecture

At least one method, apparatus and system disclosed involves circuit layout for an integrated circuit device comprising an asymmetrically placed metal formation. A design for an integrated circuit device is received. The design comprises at least one functional cell. A first metal formation is placed asymmetrically about a first cell boundary of the functional cell for providing additional space for routing.

Method, apparatus, and system for offset metal power rail for cell design

A multi-layer integrated circuit structure includes (among other components) a first layer having gate conductors, a second layer having M0 conductors, a third layer having M1 conductors, and a fourth layer having M2 conductors. The M0 and M2 conductors are perpendicular to the gate conductors, and parallel to each other. The M1 conductors connect the M0 conductors to the M2 conductors. The gate conductors are positioned in the first layer in the same locations in the horizontal direction. The M1 conductors are positioned in the third layer in a different location in the horizontal direction that is different from the locations of the gate conductors, so that the M1 conductors do not overlap any of the gate conductors, solving a substantial routing challenge for the input and output contacts.

Circuit design having aligned power staples

At least one method, apparatus and system disclosed involves providing a functional cell for a circuit layout for an integrated circuit device. A determination as to a first location for a two-dimensional portion of a first power rail in a functional cell is made. A first portion of the first power rail is formed in a first direction. A second portion of the first power rail is formed in a second direction in the first location for the two-dimensional portion.

Method, apparatus, and system for two-dimensional power rail to enable scaling of a standard cell

A semiconductor structure includes a substrate having a plurality of semiconductor devices disposed therein. A dielectric layer is disposed over the substrate. A plurality of substantially parallel metal lines are disposed in the dielectric layer. The metal lines include active lines for routing signals to and from the devices, and dummy lines which do not route signals to and from the devices. Signal cuts are disposed in the active lines. The signal cuts define tips of the active lines. Assist cuts are disposed exclusively in the dummy lines and do not define tips of the active lines. The assist cuts are located proximate the signal cuts such that a first density of assist cuts and signal cuts in an area surrounding the signal cuts is substantially greater than a second density of signal cuts alone in the same area.

Assist cuts disposed in dummy lines to improve metal signal cuts in active lines of a semiconductor structure

Methods for performing design rule checking of a circuit design are provided. The methods include, for instance: providing a circuit design for an integrated circuit layer, in which the circuit design includes a plurality of design lines oriented in a particular direction; and automatically performing a design rule check of the circuit design, which may include forming a verification pattern for the circuit design, the verification pattern comprising a plurality of verification lines and a plurality of verification regions, wherein one or more verification regions are associated with and connected to one verification line of the plurality of verification lines, and checking the verification pattern for any verification line overlapping a verification region. The circuit design may be considered to fail the design rule check if an end of one verification line overlaps any verification region associated with another verification line of the verification pattern.

Methods of design rule checking of circuit designs

At least one method, apparatus and system disclosed involves circuit layout for an integrated circuit device. A design for an integrated circuit device is received. The design comprises a functional cell. A first substitute functional cell for a first value of shift of a set of routing tracks respective to the boundary of the functional cell is provided. The first substitute functional cell comprises at least one pin moved by an amount of the first value. A determination is made as to whether an amount of shift of the set of routing tracks corresponds to the first value. The functional cell is replaced with the first substitute functional cell in response to a determination that the amount of shift of the set of routing tracks corresponds to the first value.

Method, apparatus, and system for improved standard cell design and routing for improving standard cell routability

A method of forming a pattern for interconnect lines in an integrated circuit includes providing a structure having a first lithographic stack, a mandrel layer and a pattern layer disposed over a dielectric stack. Patterning the structure to form mandrels in the mandrel layer and disposing a spacer layer over the mandrels. Etching the spacer layer to form spacers disposed on sidewalls of the mandrels. The spacers and mandrels defining beta and gamma regions. A beta region includes a beta block mask portion and a gamma region includes a gamma block mask portion of the pattern layer. The method also includes etching a beta pillar over the beta block mask portion and etching a gamma pillar over the gamma block mask portion. The method also includes etching the structure to form a pattern in the pattern layer, the pattern including the gamma and beta block mask portions.

Method of forming self aligned continuity blocks for mandrel and non-mandrel interconnect lines

Growing community of inventors

Cupertino, CA, United States of America

Lei Yuan