Altera Corporation

Jds Uniphase Corporation

Lumentum Operations LLC

Lei Xu

James Yonghong Guo

Jay A Skidmore

Benjamin Thomas Cope

Kulwinder Singh Dhanoa

Richard L Duesterberg

Edmund L Wolak

Michael Philip Fitton

Jihua Du

Kellie Marks

Martin Langhammer

Robert J Lang

Steven Perry

Volker Mauer

Tae Kyun Kim

Marc K Von Gunten

Kuochou Tai

Michael Fitton

Prasad Yalamanchili

Shahin Gheitanchi

Jeffrey P Zack

Nina D Morozova

Donald C Hargreaves

Sharifuddin Sapuan Sahori

Jane Cheng

Hilary Clarke

Christopher L Hart

William Bardy

The invention relates to wavelength stabilization and wavelength multiplexing of multiple high-power multi-mode semiconductor lasers. The lasers are wavelength-stabilized in free space using multi-peak output reflectors to wavelength-lock their output at different reflection wavelength in dependence on operating conditions, to reduce output reflectivity required for locking and increase output power. Selecting output reflectors having different non-overlapping sets of reflectivity peaks for different lasers or groups of lasers enables combining their output by wavelength multiplexing.

Wavelength locking and multiplexing of high-power semiconductor lasers

The present disclosure provides advantageously flexible and effective methods, circuits and systems for digital predistortion. In one embodiment, a predistortion component circuit includes multiple configurable delay line pairs and corresponding configurable look-up tables. Each configurable delay line pair includes a first delay line for delaying an input data signal to provide a delayed input and a second delay line for delaying an input magnitude signal to provide a delayed input magnitude. Each configurable look-up table receives the delayed input magnitude from, and outputs a look-up value for, an associated delay line pair of the plurality of configurable delay line pairs. Other embodiments, aspects and features are also disclosed herein.

Apparatus and methods for digital predistortion

Various structures and methods are disclosed related to efficiently accessing a memory for a particular application. An embodiment of the present invention utilizes characteristics of an access pattern for a particular application to provide a more efficient organization of data in a memory. In one embodiment, the predictability in access needs for a particular application is exploited to provide a data organization method for organizing data in an SDRAM memory to support efficient access. In one embodiment, the particular application is operation under the Long Term Evolution ('LTE') standard for wireless communications. In one embodiment, associated hardware and methods are provided to, when necessary, reorder read commands and, when necessary, reorder data read from memory so that at least some of the time overhead for accessing one row can be hid behind an access of another row.

SDRAM memory organization and efficient access

A laser diode subassembly is disclosed, in which dichroic reflectors are disposed sequentially one after another forming an array or stack, each reflector having a sequential array index. An array of laser diode emitters is provided, each emitter having a sequential array index. Individual reflectors of the array redirect laser sub-beams from individual laser diode emitters having same array indices, to propagate via dichroic reflectors having higher array indices, so as to form a combined optical beam. A common partial reflector may be used for the laser diode emitters instead of individual wavelength selective reflectors for each laser diode emitter.

Laser diode subassembly and method of generating light

Systems and methods are disclosed for reducing memory usage and increasing the throughput in variable-size Fast Fourier Transform (FFT) architectures. In particular, 3D symmetric virtual memory is disclosed to exploit the structure inherent in variable-size FFT computations. Data samples may be written to and read from the 3D symmetric virtual memory in a specific sequence of coordinates that exploits the structure inherent in variable-size FFT computations. Memory locations in the 3D symmetric virtual memory may be mapped to memory address in a 1D buffer using an address generation circuit.

3D memory based address generator for computationally efficient architectures

A method includes identifying a signal peak from an input signal. The signal peak may be detected with peak detection circuitry. A serial division operation may be performed on the identified signal peak value with serial division circuitry to obtain a scaling factor. The peak detection circuitry may identify an additional signal peak from the input signal concurrently with the serial division operation. The serial division operation may be halted if the additional identified signal peak is greater than the previous identified signal peak. Another serial division operation may be performed based on the additional identified signal peak.

Circuitry and techniques for calculating scaling factors for crest factor reduction

Multi-mode diode emitters are stacked in a staircase formation to provide a spatially-multiplexed output. Improved coupling efficiency is achieved by providing tilted collimated output beams that determine an effective step height of the stepped structure. Since the effective step height is dependent on the tilt angle, a variable number of emitters can be used inside packages having a same physical step height, while still attaining high coupling efficiency.

High-brightness spatial-multiplexed multi-emitter pump with tilted collimated beam

Systems and methods are disclosed for interfacing between hard logic elements and soft logic elements implemented on an integrated device. In particular, a configurable interface is provided that includes interconnects between hard logic and soft logic, which enable signals to be selectively routed between the inputs and outputs of hard logic blocks and soft logic modules. The interconnects allow for certain hard logic blocks to be bypassed in favor of soft logic functionality. Moreover, the interconnects allow soft logic to augment the processing of hard logic blocks, e.g., by providing additional signals to the hard logic block.

Systems and methods for interfacing between hard logic and soft logic in a hybrid integrated device

Efficient and scalable circuitry for performing Cholesky decomposition is based on two types of processing elements. A first type of processing element provides inverse square root and multiplication operations. A second type of processing element includes a first computation path for outputting an inner product difference element and a second computation path for outputting an inner product element. Processing elements of the first and second type may be cascaded to achieve a decomposition of a matrix of an arbitrary size. The circuitry is flexible to allow different throughput requirements, and can be optimized to reduce latency and resource consumption.

Cholesky decomposition in an integrated circuit device

Matrix operations are simplified by precalculating and storing certain portions of the operation. This reduces the computational burden, while requiring a modest increase in memory usage. The operations may be performed in a Multiple-Input/Multiple-Output ('MIMO') configuration of an LTE system, where a number of equalizer functions require matrix operations such as derivation of a covariance matrix, which involves matrix multiplication, as do other operations. The operations may be performed on a programmable integrated circuit device configured for that purposes.

Matrix operations for communications channel

A method, circuit, and a system for performing digital predistortion are disclosed. Digital predistortion may be used to compensate for or null the distortion caused by power amplifiers. The distortion of power amplifiers is usually larger at higher magnitudes or powers, and therefore, a larger percentage of the samples collected for the digital predistortion may be of higher magnitude or power. At least one sample of lower magnitude or power may be ignored or not collected. Accordingly, fewer samples can be used to perform digital predistortion, thereby allowing digital predistortion to be performed more quickly and efficiently with fewer resources.

Digital predistortion (DPD) method and system for selecting at least one data sample

A specialized processing block such as a DSP block may be enhanced by including direct connections that allow the block output to be directly connected to either the multiplier inputs or the adder inputs of another such block. A programmable integrated circuit device may includes a plurality of such specialized processing blocks. The specialized processing block includes a multiplier having two multiplicand inputs and a product output, an adder having as one adder input the product output of the multiplier, and having a second adder input and an adder output, a direct-connect output of the adder output to a first other one of the specialized processing block, and a direct-connect input from a second other one of the specialized processing block. The direct-connect input connects a direct-connect output of that second other one of the specialized processing block to a first one of the multiplicand inputs.

Specialized processing block for programmable integrated circuit device

The invention relates to sources of optical radiation wherein polarized radiation from first and second rows of light emitters is first collimated and combined into two combined beam using first and second rows of collimating and beam re-directing elements, respectively, and then polarization multiplexed to form a polarization-multiplexed output beam. In order to reduce the footprint, emitters of the first and second emitter rows are disposed in an interleaved, staggered arrangement, and the second row of collimating and beam re-directing elements is disposed in a space between the first emitter row and the first row of collimating and beam re-directing elements.

Beam combining light source

Embodiments of the present invention provide an apparatus and method for crest factor reduction, in which an input time domain signal is clipped to generate a clipped signal and a difference signal, and processing operations are carried out on the difference signal, before the processed difference signal is combined with the clipped signal to generate an output time domain signal.

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High Wycombe, United Kingdom

Lei Xu