Micron Technology Incorporated

Lei Wei

Kevin Lee Baker

Hongqi Li

Adam Thomas Barton

Fabio Pellizzer

Rajasekhar Venigalla

Karthik Sarpatwari

Nevil N Gajera

Lingming Yang

Pengyuan Zheng

Efe Sinan Ege

Don Koun Lee

Some embodiments include an arrangement having a memory tier with memory cells on opposing sides of a coupling region. First sense/access lines are under the memory cells, and are electrically connected with the memory cells. A conductive interconnect is within the coupling region. A second sense/access line extends across the memory cells, and across the conductive interconnect. The second sense/access line has a first region having a second conductive material over a first conductive material, and has a second region having only the second conductive material. The first region is over the memory cells, and is electrically connected with the memory cells. The second region is over the conductive interconnect and is electrically coupled with the conductive interconnect. An additional tier is under the memory tier, and includes CMOS circuitry coupled with the conductive interconnect. Some embodiments include methods of forming multitier arrangements.

Multitier arrangements of integrated devices, and methods of forming sense/access lines

Methods, systems, and devices for efficient fabrication of memory structures are described. A multi-deck memory device may be fabricated using a sequence of fabrication steps that include depositing a first metal layer, depositing a cell layer on the first metal layer to form memory cells of the first memory deck, and depositing a second metal layer on the cell layer. The second metal layer may be deposited using a single deposition process rather than using multiple deposition processes. A second memory deck may be formed on the second metal layer such that stacked memory cells from the first and second deck share the use of the second metal layer. Using a single deposition process for the second metal layer may decrease the quantity of fabrication steps used to fabricate the multi-deck memory array and reduce or eliminate the exposure of the cell material to metal etchants.

Efficient fabrication of memory structures

Methods, systems, and devices for reduced resistivity for access lines in a memory array are described. A first metal layer may be formed above a via that is configured to couple an access line of a memory array with a corresponding driver. The first metal layer may be oxidized, and then a second metal layer may be formed above the oxidized first metal layer. One or more access lines of the memory device may be formed from the second metal layer, the oxidized first metal layer, or both.

Reduced resistivity for access lines in a memory array

A memory system may include separate amounts or types of resistive material that may be deposited over memory cells and conductive vias using separate resistive layers in the access lines. A first resistive material layer may be deposited over the memory cells prior to performing an array termination etch used to deposit the conductive via. The array termination etch may remove the first resistive material over the portion of the array used to deposit the conductive via. A second resistive material layer may be deposited after the etch has occurred and the conductive via has been formed. The second resistive material layer may be deposited over the conductive via.

Memory with optimized resistive layers

An example apparatus includes a three-dimensional (3D) memory array including a sense line and a plurality of vertical stacks. Each respective on of the vertical stacks includes a different respective portion of the sense line, a first memory cell coupled to that portion of the sense line, a second memory cell coupled to that portion of the sense line, a first access line coupled to the first memory cell and a second access line coupled to the second memory cell. The first and second access lines are perpendicular to the sense line.

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Boise, ID, United States of America

Lei Wei