Samsung Electronics Co., Ltd.

Halliburton Energy Services, Inc.

Lei Wang

Ilia Ovsiannikov

Joseph H Hassoun

Ali Shafiee Ardestani

Yibing Michelle Wang

Sehwan Lee

Joonho Song

Jun-Woo Jang

Yuecheng Li

Gordon Layne Moake

Jeffrey James Crawford

Paravastu Badrinarayanan

Michel LeBLANC

Jiaxin Wang

A neural processor. In some embodiments, the processor includes a first tile, a second tile, a memory, and a bus. The bus may be connected to the memory, the first tile, and the second tile. The first tile may include: a first weight register, a second weight register, an activations buffer, a first multiplier, and a second multiplier. The activations buffer may be configured to include: a first queue connected to the first multiplier and a second queue connected to the second multiplier. The first queue may include a first register and a second register adjacent to the first register, the first register being an output register of the first queue. The first tile may be configured: in a first state: to multiply, in the first multiplier, a first weight by an activation from the output register of the first queue, and in a second state: to multiply, in the first multiplier, the first weight by an activation from the second register of the first queue.

Neural processor

The present disclosure describes gain stabilization techniques for scintillation devices which do not require use of an intrinsic reference radiation source. Reference light pulses are emitted into the scintillation device to obtain a signal having a given magnitude. The magnitude of the signal is compared to the magnitude of a reference signal computed as a function of temperature and a degradation factor. A gain adjustment is computed which causes the magnitude of the signal to match the target reference magnitude. The gain adjustment is then used to adjust the system gain so that subsequent output signal amplitudes, measured when energetic photons interact in the scintillator, always correspond to the same energy.

Sourceless gain stabilization for scintillation counting tools

A multichannel data packer includes a plurality of two-input multiplexers and a controller. The plurality of two-input multiplexers is arranged in 2rows and N columns in which N is an integer greater than 1. Each input of a multiplexer in a first column receives a respective bit stream of 2channels of bit streams. Each respective bit stream includes a bit-stream length based on data in the bit stream. The multiplexers in a last column output 2channels of packed bit streams each having a same bit-stream length. The controller controls the plurality of multiplexers so that the multiplexers in the last column output the 2channels of bit streams that each has the same bit-stream length.

Hardware channel-parallel data compression/decompression

In some examples, a computer-readable medium stores executable code which, when executed by a processor, causes the processor to obtain a threshold pulse rate that is based on an average pulse rate of a gamma radiation detector tool and on a desired probability that the threshold pulse rate will not be exceeded by the gamma radiation detector tool. The code also causes the processor to identify instances of pulse from the gamma radiation detector tool that do not exceed the threshold pulse rate, and output an indication of the identified instances of pulses for use in a measurement-while-drilling application.

Probabilistically distinguishing between true and false scintillator pulses

An N&#xd7;N multiplier may include a N/2&#xd7;N first multiplier, a N/2&#xd7;N/2 second multiplier, and a N/2&#xd7;N/2 third multiplier. The N&#xd7;N multiplier receives two operands to multiply. The first, second and/or third multipliers are selectively disabled if an operand equals zero or has a small value. If the operands are both less than 2, the second or the third multiplier are used to multiply the operands. If one operand is less than 2and the other operand is equal to or greater than 2, the first multiplier is used or the second and third multipliers are used to multiply the operands. If both operands are equal to or greater than 2, the first, second and third multipliers are used to multiply the operands.

Signed multiplication using unsigned multiplier with dynamic fine-grained operand isolation

A data-sparsity homogenizer includes a plurality of multiplexers and a controller. The plurality of multiplexers receives 2bit streams of non-homogenous sparse data in which the non-homogenous sparse data includes non-zero value data clumped together. The plurality of multiplexers is arranged in 2rows and N columns. Each input of a multiplexer in a first column receives a respective bit stream of the 2bit streams of non-homogenized sparse data, and the multiplexers in a last column output 2bit streams of sparse data that is more homogenous than the non-homogenous sparse data of the 2bit streams. The controller controls the plurality of multiplexers so that the multiplexers in the last column output the 2channels of bit streams of sparse data that is more homogeneous than the non-homogenous sparse data of the 2bit streams.

Homogenizing data sparsity using a butterfly multiplexer

A processor includes a register, a non-zero weight value selector and a multiplier. The register holds a first group of weight values and a second group of weight values. Each group of weight values includes at least one weight value, and each weight value in the first group of weight values corresponding to a weight value in the second group of weight values. The non-zero weight value selector selects a non-zero weight value from a weight value in the first group of weight values or a non-zero weight value in the second group of weight values that corresponds to the weight value in the first group of weight values. The multiplier multiplies the selected non-zero weight value and an activation value that corresponds to the selected non-zero weight value to form an output product value.

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Burlingame, CA, United States of America

Lei Wang