Cirrus Logic Inc.

Lei Wang

Wai Laing Lee

Edwin De Angel

Chung-Kai Chow

Joel W Page

Hong Helena Zheng

Axel Thomsen

Dan Bernard Kasha

Aryesh Amar

Sherry Xiaohong Wu

Stephen Bily

A network arrangement uses a poll select control protocol and a loop back arrangement at each node for equalizing transmission delay from each node to a central station. Delays at each node can be adjusted to start timing in response to a broadcast signal indicating an amount of delay to be applied from the start of a synchronization interval to the beginning of transmission of data collected at the nodes. The arrangement is particularly useful in the field of data acquisition and particularly in the area of seismic sensing.

Network synchronization

A power on reset circuit, preferably for an integrated circuit, detects application of voltage, starts a phase locked loop one application of voltage is detected but inhibits all clock used for digital logic operations until voltage stability is achieved. If a switched converter is used, the duty cycle of the switched converter is held at unity for a period of time before it is set to that needed to achieve the desired chip operating voltage. Clocks controlling other circuits can be released in stages after the duty cycle of the switched converter is set to its operating voltage level.

Power on reset techniques for an integrated circuit chip

A signal processing integrated circuit has having a chopper stabilized, multistage, feedforward amplifier and a delta sigma analog to digital converter. Filtering of the output of the output from the analog to digital converter comprises a sincfilter and a sincfilter. The sincfilter may be bypassed. A rough buffer permits quick charging of a sample and hold capacitor during part of the charge cycle and slower but more accurate charging during the remainder of the charge cycle.

Techniques for signal measurement using a conditionally stable amplifier

A sinc filter is implemented by partitioning 1 bit wide incoming data into multibit words. The multibit words are multiplied by respective coefficient sets. Some multibit words are twisted by inverting the bit order and the multiplied using the same coefficient sets used for untwisted words. Multiplications are implemented using either look up tables or logic and the filter is implemented using only shifts and additions. The sinc filter is particularly useful applications in the field of data acquisition and particularly in the area of seismic sensing.

Sinc filter using twisting symmetry

A buffer arrangement uses separate amplifiers for handling for positive going signal transitions and for negative going signal transitions respectively. A comparator detects the direction of transition and a switching element connects signal input lines in the appropriate sense to the respective amplifiers based on the output of the comparator. This permits amplifiers optimized for positive or negative going transitions to be used. The output of the amplifiers can be connected across a sampling capacitor

Techniques for implementing a rough buffer for charging a sampling capacitor

In accordance with the present invention complementary P-channel and N-channel input pairs of transistors form in an op amp. Two sets of such pairs are provided so that a transconductance range of each set of pairs is different. By combining the outputs of each of the sets of P-channel and N-channel pairs, a transconductance glitch is reduced in half.

Operational amplifier with multiple complementary P-channel and N-channel input pairs to reduce transconductance variation

A data acquisition system has a central station connected to a plurality of nodes over a network. Each node is connected to receive signals from one or more sensors ad each is configured to have substantially the same transmission delay to said central station. The central station is configured to notify all nodes of an event time at which a data event, such as a seismic shot, occurred.

System and techniques for seismic data acquisition

A phase shifter is implemented using a polyphase filter. The filter is preferably a linear phase Finite Impulse Response (FIR) filter. The amount of delay imparted by the phase shifter is determined by a particular set of coefficients selected from a plurality of such coefficients. Storage requirements are reduced by taking advantage of symmetries in the coefficients for the filters. Memory requirements are further reduced by partitioning the polyphase filter into two polyphase filters and using one to set a rough delay amount and the other to set a fine delay amount between rough delay amount settings. The particular amount of delay may be set by an external synchronization signal.

Linear phase FIR sinc filter with multiplexing

A decimation filter implements selective decimation ratios by arranging a plurality of sinc filters in different pipeline arrangements to produce the desired ratio. Power savings area achieved by implementing the sinc filters as FIR sinc filters and by implementing multiplications using look up tables. One approach uses a fixed first stage filter and one or more second stage sinc filters selected from the group comprising two 4,order, 5 tap sinc filters, a 4,order, 9 tap sinc filter; a 5,order, 6 tap sinc filter and a 6,order 7 tap sinc filter. The sinc filter is particularly useful applications in the field of data acquisition and particularly in the area of seismic sensing.

Sinc filter with selective decimation ratios

A switched converter uses two series connected complementary CMOS devices and has a square wave source for activating one CMOS device while deactivating the other; and a break before make circuit connected between the square wave source and said complementary CMOS devices to ensure that one device is substantially completely off before the other device turns on. The switched converter is programmable as to frequency, phase and duty cycle.

Noise management using a switched converter

A multiply add carry (MAC) circuit correctly determines the value of a carry bit when an operation X*Y&plus;Z is undertaken, where X, Y and Z are real numbers and where an accumulator and rounding are utilized. The circuit (1) determines if the product X*Y is negative, (2) determines if the value in the accumulator is negative, (3) determines if a round bit propagates all the way to the most significant bit (MSB) position, (4) determines if the result X*Y&plus;Accumulator&plus;round is negative; and (5) determines a correct carry bit based on the other determinations.

Correct carry bit generation

A high performance test signal generator uses a digital to analog converter which converts an N-bit digital signal, such as provided by a computer waveform generator or by a CDROM into an M-bit upsampled digital signal. The M-bit digital signal is applied to an M-bit digital to analog converter to produce an analog output signal. The analog output signal is sampled and fed back across, the discrete time/continuous time interface to the input of the conversion circuit. The test signal generator has very low power consumption yet meets very strict noise and linearity requirements. The test signal generator can be used for testing seismic sensors such as geophones or hydrophones.

Digitally driven analog test signal generator

A multi-bit digital to analog converter uses both discrete time and continuous time processing to produce an analog output signal. The analog output signal is sampled and fed back across the discrete time/continuous time interface to the input of the conversion circuit. In one implementation, the discrete time processing uses an integrator chain of switched capacitor integrators and a switched capacitor low pass filter. The continuous time processor is a 2 pole low pass filter. A finite impulse response filter can precede the discrete time processing. A plurality of analog output sampling arrangements can be selectively applied accommodate a variety of operational conditions.

Multibit digital to analog converter with feedback across the discrete

A integrated circuit digital to analog converter converts an M-bit digital signal to an analog output signal. The analog output signal can be used to drive external devices such as an off-chip driver. The output of the external device is sampled and fed back across the discrete time/continuous time interface on the chip to the input of the analog to digital converter. Taking the feedback point after the external device ensures relatively high performance for noise and linearity using relatively low performance components, both on and off the chip.

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College Station, TX, United States of America

Lei Wang