Nxp USA, Inc.

Freescale Semiconductor,inc.

University of Shanghai for Science and Technology

Lei Tian

Xiaowen Wu

Yongqin Liang

Ricardo Pureza Coimbra

Hong Yang Wang

Xi Lu

Jie Jin

Marcos Mauricio Pelicia

Luis Enrique Del Castillo

Shubao Guo

Zhenguo Sun

Hanguang Liu

Jingjian Zhang

Jiawei Huang

A low voltage differential driver includes a first driver, a second driver, and an output driver. The output driver is configured to provide an output between a first output node and a second output node, and includes a current source, a first branch, and a second branch. The current source is configured to provide a source current. The current source is connected with a parallel arrangement of the first branch and the second branch. The first switch and the second switch are respectively controlled by a first switch circuit and a second switch circuit which together comprise the first driver. The third switch and the fourth switch are respectively controlled by a third switch circuit and a fourth switch circuit which together comprise the second driver. Each of the first to fourth switch circuits is connected between the upper node and the lower node.

Low voltage differential signaling driver

A single-inductor, multiple-output, DC-DC converter has regulation circuitry that controls switches to alternately charge at least two capacitors associated with at least two DC output voltages via the single inductor from a DC input port. The regulation circuitry determines whether the DC-DC converter is operating in continuous conduction mode (CCM) or discontinuous conduction mode (DCM). In CCM mode, the regulation circuitry regulates the charging duty cycle for a first output voltage and generates the initial charging duty cycle for regulating each other output voltage by scaling the first output voltage duty cycle. In DCM mode, the regulation circuitry independently regulates the charging duty cycles for each output voltage and stores each duty cycle to be used for the next charging period for the same output voltage. The regulation circuitry detects and handles undershoot and overshoot conditions to accelerate recovery at the output ports.

Single-inductor, multiple-output, DC-DC converter

To solve the technical problem of the incapacity to perform a quantitative matching design of residual compressive stress in the process of prior structural cold working-residual compressive stress design, the invention provides a method of structural cold working-residual compressive stress distribution quantitative matching design, characterized by treating the fatigue strength of a mechanical structure and parts as a field, and matching a structural stress field and a fatigue strength field organically, to quantitatively match the residual compressive stress in conjunction with characteristics of the cold working process. The method specifically includes determination of the maximum stress amplitude and a gradient distribution thereof at a dangerous position of the structure, determination of an ideal fatigue strength distribution of the dangerous cross-section of the structure, determination of a fatigue strength field according to curves of end quenching tests for material and a requirement for heat treatment, determination of the limit of the residual compressive stress according to characteristics of the structural cold working process, and determination of an actual residual compressive stress distribution of the dangerous cross-section in conjunction with cold working and the fatigue strength distribution.

Method of structural cold working-residual compressive stress distribution quantitative matching design

Regulation systems and methods use a first regulator and a tracking second regulator. The first regulator receives a reference voltage and generates a first voltage output based upon the reference voltage, which is coupled as a back-bias voltage to a first load region within the integrated circuit. The first regulator also receives a sampled version of the first voltage output as feedback. A second regulator receives the first sampled voltage output and generates a second voltage output. The second regulator also receives a sampled version of the second voltage output as feedback. During operation, the second voltage output tracks (e.g., by a symmetry ratio) the first voltage output and is coupled as a back-bias voltage to a second load region within the integrated circuit. Further, switched-capacitor operation can be implemented, and clock frequency can be adjusted based upon the first sampled voltage output to reduce power consumption.

Back-biasing regulation system and method for integrated circuits

A single-inductor DC-DC converter generates two DC output voltages at two capacitors. The converter selectively transfers energy from a battery to the inductor or from the inductor to a selected capacitor. While the converter is still settling, the converter is regulated based on only the more deficient DC output voltage. After the converter has already settled, the converter is regulated based on the common-mode voltage for both DC output voltages. By regulating the still-settling converter based on only the more deficient DC output voltage, instead of the common-mode voltage, even greater deficiencies in that already more-deficient DC output voltage are avoided.

Single inductor, multiple output DC-DC converter

One example discloses A differential receiver, including: a set of high voltage differential inputs configured to receive a first range of differential voltages; a first level shifter configured to generate a second range of differential voltages that are less than the first range of differential voltages; and a first low voltage differential comparator coupled to the first level shifter and configured to generate a first differential receiver output based on the second range of differential voltages.

Differential receiver

A DC-DC power converter converts a DC input voltage at an input node into a DC output voltage at an output node. The converter has a main control loop that generates control signals used to control series-connected p-type and n-type switches that selectively connect an inductor to the input node or to ground while operating the converter in either a continuous-conduction mode (CCM) or a discontinuous-conduction mode (DCM). Zero-crossing detection (ZCD) circuitry detects when the inductor current reaches zero and generates a ZCD control signal used to control the n-type switch to inhibit negative inductor currents during the DCM mode. Overshoot-protection (OP) circuitry detects when the DC output voltage gets too high and generates an OP control signal used to control the n-type switch to inhibit overshoot conditions at the output node that can result from CCM-to-DCM mode transitions and from sudden reductions in output current loading.

DC-DC power converter with overshoot protection

A level shifter in a primary voltage domain has a control module receiving an input signal from a secondary voltage domain for controlling operation of the level shifter. The control module includes a complementary pair of transistors and a first native transistor connected in a series current conduction path in the primary voltage domain. The complementary pair of transistors have gates connected to receive the input signal and the first native transistor has a gate connected to limit to a leakage current the current in the series current conduction path.

Voltage level shifter

A CMOS temperature detection circuit includes a start-up circuit for generating a start-up voltage (VN), and a proportional to absolute temperature (PTAT) current generator coupled to the start-up circuit for generating a PTAT current. The start-up voltage turns on the PTAT current generator, and the PTAT current generator uses the sub-threshold characteristics of CMOS to generate the PTAT current. A PTAT voltage generator coupled to the PTAT current generator receives the PTAT current and generates a PTAT voltage and an inverse PTAT voltage (VBE). A comparator circuit coupled to the voltage generator compares the inverse PTAT voltage to first and second alarm limits, which are defined using the generated PTAT voltage, and generates an alarm signal based on the comparison results.

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Shanghai, China

Lei Tian