Globalfoundries Inc.

Globalfoundries U.S. Inc.

Lei Sun

Ruilong Xie

Xunyuan Zhang

Wenhui Wang

Ryan Ryoung-Han Kim

Hui Zang

Lars W Liebmann

Daniel Chanemougame

Guoxiang Ning

Xuelian Zhu

Obert Reeves Wood, Ii

Yulu Chen

Bipul C Paul

Youngtag Woo

Shao Beng Law

Heimanu Niebojewski

Genevieve Beique

Erik A Verduijn

Chanro Park

Guillaume Bouche

Frank Wilhelm Mont

Francis Goodwin

Min Gyu Sung

Laertis Economikos

Jia Zeng

Linus Jang

Jason Cantone

Seowoo Nam

John H Zhang

Jed Hickory Rankin

Haiting Wang

Yongan Xu

Yi Qi

Azat M Latypov

Nicholas V Licausi

Roderick Alan Augur

Yong Liang

Sean Xuan Lin

Hsien-Ching Lo

Geng Han

Tamer Coskun

Daniel James Dechene

Meixiong Zhao

Zhengqing John Qi

Erfeng Ding

Pawitter Mangat

Craig D Higgins

Yongiun Shi

Oleg Kritsun

Erik Verduijn

One illustrative integrated circuit (IC) product disclosed herein includes a first conductive source/drain contact structure of a first transistor with an insulating source/drain cap positioned above at least a portion of an upper surface of the first conductive source/drain contact structure and a gate-to-source/drain (GSD) contact structure that is conductively coupled to the first conductive source/drain contact structure and a first gate structure of a second transistor. In this example, the product also includes a gate contact structure that is conductively coupled to a second gate structure of a third transistor, wherein an upper surface of each of the GSD contact structure and the gate contact structure is positioned at a first level that is at a level that is above a level of an upper surface of the insulating source/drain cap.

Gate contact structures and cross-coupled contact structures for transistor devices

Methods pattern a sacrificial material on an etch mask into mandrels using optical mask lithography, form a conformal material and a fill material on the mandrels, and planarize the fill material to the level of the conformal material. Such methods pattern the fill material into first mask features using extreme ultraviolet (EUV) lithography. These methods partially remove the conformal material to leave the conformal material on the sidewalls of the mandrels as second mask features. Spaces between the first mask features and the second mask features define an etching pattern. The spacing distance of the mandrels is larger than the spacing distance of the second mask features. Such methods transfer the etching pattern into the etch mask material, and subsequently transfer the etching pattern into an underlying layer. Openings in the underlying layer are filled with a conductor to form wiring in the etching pattern.

Hybrid optical and EUV lithography

Structures that include interconnects and methods of forming structures that include interconnects. A first interconnect is formed in a first trench in an interlayer dielectric layer, and a second interconnect in a second trench in the interlayer dielectric layer. The second interconnect is aligned along a longitudinal axis with the first interconnect. A dielectric region is arranged laterally arranged between the first interconnect and the second interconnect. The interlayer dielectric layer is composed of a first dielectric material, and the dielectric region is composed of a second dielectric material having a different composition than the first dielectric material.

Interconnects separated by a dielectric region formed using removable sacrificial plugs

The present disclosure relates to semiconductor structures and, more particularly, to an extreme ultraviolet (EUV) lithography mask and methods of manufacture. The EUV mask structure includes: a reflective layer; a capping material on the reflective layer; a buffer layer on the capping layer; alternating absorber layers on the buffer layer; and a capping layer on the top of the alternating absorber layers.

Extreme ultraviolet (EUV) lithography mask

Disclosed are embodiments of a multi-layer stack and photolithography methods and systems that employ such a stack. The disclosed multi-layer stacks include a photoresist layer on an underlayer. The photoresist layer and underlayer are made of different materials, which are selected so that valence and conduction band offsets between the underlayer and photoresist layer create an effective electric field (i.e., so that the stack is 'self-biased'). When areas of the photoresist layer are exposed to radiation during photolithography and the radiation passes through photoresist layer and excites electrons in the underlayer, this effective electric field facilitates movement of the radiation-excited electrons from the underlayer into the radiation-exposed areas of the photoresist layer in a direction normal to the interface between the underlayer and the photoresist layer. Movement of the radiation-excited electrons from the underlayer into the radiation-exposed areas of the photoresist layer improves photoresist layer development and pattern resolution.

Photolithography methods and structures that reduce stochastic defects

A method of fabricating interconnects in a semiconductor device is provided, which includes forming a metallization layer and depositing a hardmask layer over the metallization layer. A dielectric layer is deposited over the hardmask layer and an opening is formed in the dielectric layer to expose the hardmask layer. The exposed hardmask layer in the opening is etched to form an undercut beneath the dielectric layer. A metal shoulder is formed at the undercut, wherein the metal shoulder defines an aperture dimension used for forming a via opening extending to the metallization layer.

Controlling back-end-of-line dimensions of semiconductor devices

Methods for forming a cut between interconnects and structures with cuts between interconnects. A layer is patterned to form first, second, and third features having a substantially parallel alignment with the second feature between the first feature and the third feature. A sacrificial layer is formed that is arranged between the first and second features and between the second and third features. The sacrificial layer is patterned to form a cut between the first and second features from which a portion of the sacrificial layer is fully removed and to form a cavity in a portion of the sacrificial layer between the second and third features. A dielectric layer is formed inside the cut between the first and second features. After depositing the section of the dielectric material and forming the dielectric layer, the sacrificial layer is removed.

Self-aligned cuts in an interconnect structure

One illustrative method disclosed includes, among other things, selectively forming a gate-to-source/drain (GSD) contact opening and a CB gate contact opening in at least one layer of insulating material and forming an initial gate-to-source/drain (GSD) contact structure and an initial CB gate contact structure in their respective openings, wherein an upper surface of each of the GSD contact structure and the CB gate contact structure is positioned at a first level, and performing a recess etching process on the initial GSD contact structure and the initial CB gate contact structure to form a recessed GSD contact structure and a recessed CB gate contact structure, wherein a recessed upper surface of each of these recessed contact structures is positioned at a second level that is below the first level.

Methods of forming gate contact structures and cross-coupled contact structures for transistor devices

A self-aligned quadruple patterning (SAQP) process for forming semiconductor devices utilizes a look-up table based on lithography and etch profiles to improve the critical dimension(s) of semiconductor structures such as semiconductor fins. The look-up table may include lithography and etch data, including critical dimension (CD) and sidewall angle (SWA) data for intermediate as well as final structures formed during fabrication, and may be used to improve fin CD and fin pitch in device architectures that include densely-arrayed, semi-densely arrayed and nested structures.

Self-aligned quadruple patterning pitch walking solution

The present disclosure relates to methods of protecting a structure of an integrated circuit (IC) from rework, and more particularly, to methods of protecting a structure of an IC without impacting the critical dimension or the profile of the structure. For example, a method of protecting a structure of an IC from rework may include forming a first layer on a second layer; forming one or more first openings in the first layer, the first openings exposing a top surface of the second layer; selectively growing a Group VIII metal within the one or more first openings, thereby forming one or more first plugs; forming one or more final openings in the first layer; and removing the one or more first plugs.

Methods of protecting structure of integrated circuit from rework

The present disclosure generally relates to semiconductor structures and, more particularly, to overlay mark structures and methods of manufacture. The method includes: forming an overlay mark within a layer of a stack of layers; increasing a density of an upper layer of the stack of layers, above the layer, the increased density protecting the overlay mark; and polishing the upper layer or one or more layers above the upper layer of the stack of layers.

Overlay mark structures

The disclosure is directed to methods of identifying a space within an integrated circuit structure as a mandrel space or a non-mandrel space. One method may include: identifying a space between freestanding spacers as being one of: a former mandrel space created by removal of a mandrel from between the freestanding spacers or a non-mandrel space between adjacent mandrels prior to removal of the mandrel, based on a line width roughness of the space, wherein the line width roughness represents a deviation of a width of the space from a centerline axis along a length of the space.

Methods of identifying space within integrated circuit structure as mandrel space or non-mandrel space

One integrated circuit (IC) product disclosed herein includes a first conductive source/drain contact structure of a first transistor and an insulating source/drain cap positioned above at least a portion of an upper surface of the first conductive source/drain contact structure. In one example, the product also includes a gate-to-source/drain (GSD) contact structure that is conductively coupled to the first conductive source/drain contact structure and a first gate structure of a second transistor, wherein an upper surface of the GSD contact structure is positioned at a first level that is at a level above the upper surface of the first conductive source/drain contact structure, and a CB gate contact structure that is conductively coupled to a second gate structure of a third transistor, wherein an upper surface of the CB gate contact structure is positioned at a level that is above the first level.

Extreme ultraviolet mirrors and masks used in lithography and methods for manufacturing an extreme ultraviolet mirror or mask. Initial data is obtained that includes materials and optical properties for a first intermixed layer, a second intermixed layer, a first pure layer, and a second pure layer in each of a plurality of periods of a multi-layer stack for an optical element. For multiple thicknesses for the first pure layer and multiple thicknesses for the second pure layer, a reflectivity of the multi-layer stack is determined based on the initial data, a thickness received for the first intermixed layer, and a thickness received for the second intermixed layer. One of the thicknesses for the first pure layer and one of the thicknesses for the second pure layer are selected that maximize the reflectivity of the multi-layer stack.

Extreme ultraviolet mirrors and masks with improved reflectivity

Growing community of inventors

Albany, NY, United States of America

Lei Sun