International Business Machines Corporation

Other

Elpis Technologies Inc.

Lei Shan

Jiali Wu

Daniel Joseph Friedman

Jeannine Madelyn Trewhella

Modest M Oprysko

John Ulrich Knickerbocker

Daniel Mark Dreps

Griselda Bonilla

Sungjun Chun

Rohan U Mandrekar

Dierk Kaller

Kellsie Shan

A base substrate, high-k substrate layers on the base substrate with discrete decoupling capacitors embedded, high density substrate layers on the high-k substrate layers supporting wiring and wiring spacing of less than 2 up to about 10 micron width, pitch connectivity between the upper surface of the base substrate and a lower surface of the set of high density substrate layers supports less than 50 up to about 300 micron pitch, the pitch connectivity on an upper surface of the set of high density substrate layers supports less than about 150 micron pitch. A method including attaching a set of metal posts at each contact on a lower surface of a set of high density substrate layers, attaching to a handler, attaching an interconnect layer to a base substrate, and attaching the set of high density substrate layers to the base substrate while aligning each metal post with a contact.

Electronic substrate stacking

An embodiment of the invention may include a method, and resulting structure, of forming a semiconductor structure. The method may include forming a component hole from a first surface to a second surface of a base layer. The method may include placing an electrical component in the component hole. The electrical component has a conductive structure on both ends of the electrical component. The electrical component is substantially parallel to the first surface. The method may include forming a laminate layer on the first surface of the base layer, the second surface of the base layer, and between the base layer and the electrical component. The method may include creating a pair of via holes, where the pair of holes align with the conductive structures on both ends of the electrical component. The method may include forming a conductive via in the pair of via holes.

Power decoupling attachment

An exemplary assembly includes a top circuit substrate; a bottom circuit assembly that underlays the top circuit substrate and is attached to the top circuit substrate by an adhesive layer as a stiffener, the adhesive layer, and a plurality of conductive balls. The top circuit substrate includes a plurality of upper vias that extend through the top circuit substrate. The bottom circuit assembly includes a plurality of lower vias that extend through the bottom circuit assembly. The adhesive layer includes internal connections that electrically connect the upper vias to the lower vias. The conductive balls are housed in the lower vias. The bottom circuit assembly has an elastic modulus at least six times the elastic modulus of the top circuit substrate, and has a coefficient of thermal expansion at least two times the coefficient of thermal expansion of the top circuit substrate.

Functional stiffener that enables land grid array interconnections and power decoupling

The present invention provides a substrate assembly includes at least two ceramic layers, at least two layers of one or more electrodes, at least one high dielectric constant layer, two or more holes, electrically conductive structures formed in the two or more holes, and the electrically conductive structure is physically connected to at least one of the electrodes, thereby forming a set, wherein each of the sets if physically separated from at least one of the other sets. A process includes cutting ceramic sheets, removing material from the ceramic sheets to form holes, depositing a metallic material into the holes, depositing the metallic material to form electrodes, selectively depositing a thin layer of high dielectric constant material, and firing the ceramic sheets, the metallic material, the high dielectric constant material layer, and the electrodes.

Multi-layer capacitor package

Embodiments are directed to a method of embedding a discrete component in a substrate. The method includes forming a cavity in the substrate. The method further includes inserting a discrete component into the cavity, wherein the discrete component comprises a top terminal and a bottom terminal. The method further includes positioning the discrete component within the cavity such that the top terminal is above the bottom terminal and below a front face of the substrate. The method further includes forming an intermediate conductive material within the cavity and over the top terminal. The method further includes forming a top conductive material over the intermediate conductive material such that the top conductive material is electrically coupled through the intermediate conductive material to the top terminal.

Embedding discrete components having variable dimensions in a substrate

A thermally conductive interface composition is interposed between a heat generating component and a heat dissipating component. To meet escalated heat dissipation for performance demanding devices, a thermally conductive interface composition comprises (A) A linear alkenyl organopolysiloxane containing a silicon-bonded alkenyl-terminated group or groups, (B) A branched alkenyl organopolysiloxane containing at least two silicon-bonded alkenyl groups, (C) thermally conductive fillers in a ternary particle size mixture, (D) An organohydrogenpolysiloxane containing at least two Si&#x2014;H terminated groups, (E) An addition reaction catalyst, (F) A hydroxy group-containing siloxane, (G) Alkoxy group-containing siloxanes.

Thermally conductive interface composition and use thereof

A memory module configured to connect to a slot of a data processing system. A set of tabs is connected to the module and configured to electrically connect the module to the slot and to electrically connect the module to a clock of the data processing system. The set of tabs includes a first tab, a second tab, a third tab, and a fourth tab. The first tab and the second tab are opposite the third tab and the fourth tab. The first tab comprises a positive type tab, the second tab comprises a negative type tab, the third tab comprises a positive type tab, and the fourth tab comprises a negative type tab. The first and third tabs are configured to provide a first electrical connection to the clock. The second and fourth tabs are configured to provide a second electrical connection to the clock. Together, the first, second, third, and fourth tabs comprise two dual tabs.

Redundant clock channel for high reliability connectors

A DIMM connector having reduced crosstalk includes ceramic particles having a high dielectric constant and/or composite fibers mixed into materials used for fabricating a connector housing of the DIMM connector.

Crosstalk reduction in dual inline memory module (DIMM) connectors

An integrated circuit arrangement or package includes a set of contact pads arranged in a pattern and a multi-layer conductive structure, which electrically connects the set of contact pads to at least one signal line. The conductive structure provides impedance matching between the pads and the at least one signal line.

Via and via landing structures for smoothing transitions in multi-layer substrates

An improved electrical interconnect is formed wherein a dielectric material having a controllable characteristic is applied to at least a portion of the interconnect. The controllable characteristic of the dielectric material is selectively adjustable so that the impedance of the electrical interconnect is substantially matched to at least one impedance at first and second ends of the interconnect. In this manner, an electrical discontinuity between the first and second ends of the electrical interconnect is reduced, thereby improving an electrical performance of the interconnect.

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Carmel, NY, United States of America

Lei Shan