Taiwan Semiconductor Manufacturing Comp. Ltd.

TSMC China Company Limited

Tyco Electronics (shanghai) Co., Ltd.

TSMC Nanjing Company, Limited

Micron Technology Incorporated

Te Connectivity Solutions Gmbh

Tyco Electronics Japan G.k.

Siemens Healthcare Gmbh

Te Connectivity India Private Limited

Taiwan China Company, Limited

Tyco Electronics Co., Ltd.

Lei Pan

Zhen Tang

Miranda Ma

Qingchao Meng

Tongbao Ding

Ya-Qi Ma

Tian Xia

Zhang-Ying Yan

Yaqi Ma

Yulin Feng

Ken Sakai

Kai Zhou

Pai Rajendra

Kuo-Ji Chen

Carsten Thierfelder

Daniel Lerch

Florian Hilbig

Jing Ding

Xin-Yong Wang

Qi Dong

Xing Tong

Bruno Doerrfuss

Pai R Rajendra

JunKui Hu

Ramachandra Pai B Rajendra

Huigang Guo

Tian-Yu Xie

Poorna Kale

Shao-Yu Chou

Chong Hun Yi

Huaixin Xian

Yang Zhou

Biao Pan

Weifeng Bian

Weiguo Li

Tom Morris

Stephen J Descioli

Tian (Sam) Xia

Rajendra Pai

Pai B Ramachandra Rajendra

J B Zhang

Selma Zehner

Selma Osmanlic

Stephen Descioli

Pai Rejendra

Yuhong Mao

Exemplary methods, apparatuses, and systems include a performance mode manager for controlling performance of a wireless update by selecting a performance mode using rations of allocation. The performance mode manager receives a request to initialize a file transfer from a host using wireless communication. In response to the request, the performance mode manager identifies a size of the file transfer by the memory subsystem. The performance mode manager selects a performance mode from a plurality of performance modes and allocates the available set of memory pages using the performance mode. The performance mode manager receives a file of the file transfer. The performance mode manager programs a first portion of the file at the default bit density to the first portion of memory and a second portion of the file at the reduced bit density to the second portion of memory.

Intelligent performance mode selection to manage quality of service

Methods, systems, and devices for data handling during a reflow operation are described. The method may include a memory system receiving first signaling indicating that a reflow operation is to be performed on the memory system and determining whether an amount of data stored in a first set of memory cells within one or more memory devices of the memory system satisfy a threshold. The method may further include the memory system communicating an indication of whether the memory system is ready for the reflow operation based on the amount of data satisfying the threshold.

Data handling during a reflow operation

Exemplary methods, apparatuses, and systems include an update performance manager for controlling performance of a wireless update by adjusting prioritization of internal operations for a memory subsystem. The update performance manager receives a first notification representing an initialization of a file transfer that includes an update file from a host using wireless communication. The update performance manager enters an update mode by reducing a priority of at least one internal operation of the memory subsystem in response to the first notification. The update performance manager receives the update file. The update performance manager programs the update file to memory. The update performance manager receives a second notification being a completion of the file transfer. The update performance manager resetting the priority of the at least one internal operation of the memory subsystem to a default value in response to the second notification.

Performance management using intelligent prioritization of memory operations

A sensor module includes a housing having a first cavity and a second cavity that are in communication with each other, a liquid level sensing module mounted on the housing and sensing liquid level related information when liquid flows into the second cavity, a turbidity sensing module mounted on a section of the housing having the first cavity, and a temperature sensing module integrated with the turbidity sensing module and sensing temperature related information of the liquid when the liquid flows into the first cavity. The turbidity sensing module includes a light transmitting unit and a light receiving unit that are located on opposite sides of the first cavity to allow light emitted from the light transmitting unit to pass through the first cavity and to be received by the light receiving unit.

Sensor module

A method is provided and includes the operation below: discharging electrostatic charges from a pad to a first voltage terminal through a first active region coupled to the pad and a second active region coupled between the first active region and the first voltage terminal, in which the first active region and the second active region are the same conductivity type and have different widths from each other, and the first active region and the second active region are included in a first transistor having a first breakdown voltage; and discharging the electrostatic charges through an ESD primary circuit having a first terminal coupled with the first active region and a second terminal coupled with the first voltage terminal. The ESD primary circuit has a trigger voltage lower than the first breakdown voltage.

Integrated circuit

A sensor assembly includes a housing including a cavity allowing a liquid to flow thereinto, a liquid level sensing module installed on the housing and configured to sense information related to a liquid level when the liquid is flowing into the cavity, and a turbidity sensing module installed on the housing. The turbidity sensing module includes a light emitting unit and a light receiving unit. The light emitting unit and the light receiving unit are located oppositely on an outer surface of the housing to allow a light emitted from the light emitting unit to pass through the cavity of the housing and be received by the light receiving unit.

Sensor assembly

An integrated circuit includes first to second transistors and a resistive device. The first transistor is coupled between a pad and a first voltage terminal that provides a first supply voltage. The second transistor is coupled in parallel with the first transistor. A breakdown voltage of the first transistor is different from a trigger voltage of the second transistor. The resistive device is coupled between the pad and a second voltage terminal that provides a second supply voltage higher than the first supply voltage, and operates with the second supply voltage in an electrostatic discharge (ESD) event when the first and second transistors discharge a ESD current between the pad and the first voltage terminal.

An integrated circuit includes a control circuit and first to second voltage generation circuits. The control circuit is coupled between a first voltage terminal providing a first supply voltage and a first node coupled to a first capacitive unit. The first voltage generation circuit includes at least one first transistor that has a source terminal receiving a second supply voltage, a drain terminal coupled to a second node in contact with a second capacitive unit, and a gate terminal coupled to the first node. The second voltage generation circuit is coupled to the first voltage terminal and the first and second nodes. Firstly the control circuit turns on the at least one first transistor to adjust a voltage level of the second node to have the second supply voltage. The second voltage generation circuit adjusts a voltage level of the first node to have the first supply voltage.

Integrated circuit and an operation method thereof

Technologies for storing streaming data include, in some embodiments, in response to determining that the chunk size satisfies a chunk size threshold and the streaming data is sequential data of a size that satisfies a threshold sequential data size, writing the sequential data to a first file system partition of a file system comprising a plurality of file system partitions, and in response to determining that the chunk size does not satisfy the chunk size threshold or the chunk size satisfies the chunk size threshold and the streaming data is the first type of metadata, writing the streaming data to a second file system partition of the plurality of file system partitions.

Multi-partition file system for storing video streams in a managed non-volatile memory device

A circuit includes an input circuit, a level shifter circuit and an output circuit. The input circuit is coupled to a first voltage supply, and configured to receive a first input signal, and to generate at least a second or a third input signal. The level shifter circuit is coupled to the input circuit and a second voltage supply, and configured to receive a first enable signal, the second or third input signal, and to generate a first signal responsive to the first enable signal, the second input signal or the third input signal. The level shifter circuit includes a header circuit coupled to a first node, and is configured to enable or disable the level shifter circuit responsive to the first enable signal. The output circuit is coupled to at least the level shifter circuit and the second voltage supply, and is configured to generate an output signal.

Level shifter circuit and method of operating the same

An integrated circuit (IC) includes a first power supply node configured to have a first power supply voltage level, a second power supply node configured to have a second power supply voltage level separate from the first power supply voltage level, an n-well, a bias circuit, and a level shifter. The n-well contains first and second PMOS transistors including first source/drain (S/D) terminals coupled to the first power supply node, and third and fourth PMOS transistors including second S/D terminals coupled to the second power supply node. The bias circuit includes the first PMOS transistor including a third S/D terminal coupled to the n-well and a gate coupled to the second power supply node, and the third PMOS transistor including a fourth S/D terminal coupled to the n-well and a gate coupled to the first power supply node. The level shifter includes the second and fourth PMOS transistors.

Level shifting circuit and method

Methods, systems, and devices for external power functionality techniques for memory devices are described. A memory system, which may be coupled to a first power source associated with a first voltage, may detect whether a second power source associated with a second voltage higher than the first voltage is available. The memory device may activate a functionality to use the second power source for the access operations if the second power source is available, and the memory device may then perform one or more access operations using the second voltage from the second power source based on the activated functionality.

External power functionality techniques for memory devices

An IC structure includes first and second gates, first and second source/drain regions, and an isolation region. The first and second gates each have a first portion extending along a first direction and a second portion extending along a second direction. The first source/drain regions are respectively on opposite sides of the first portion of the first gate. The second source/drain regions are respectively on opposite sides of the first portion of the second gate. The isolation region has a lower portion between a first one of the first source/drain regions and a first one of the second source/drain regions, and an upper portion partially overlapping with the second portion of first gate and the second portion of the second gate. A width of the lower portion is a less than a width of the upper portion.

Integrated circuit with active region jogs

An integrated circuit includes a middle active-region structure between a group-one active-region structure and a group-two active-region structure. The integrated circuit also includes a main circuit, a group-one circuit, and a group-two circuit. The main circuit includes at least one boundary gate-conductor intersecting the middle active-region structure. The group-one circuit includes a group-one isolation structure separating the group-one active-region structure into a first part in the group-one circuit and a second part in a first adjacent circuit. The group-two circuit includes a group-two isolation structure separating the group-two active-region structure into a first part in the group-two circuit and a second part in a second adjacent circuit.

Circuit arrangements having reduced dependency on layout environment

A Schmitt trigger circuit includes a first and second set of transistors, a first and second feedback transistor, and a first and second circuit. The first set of transistors is connected between a first voltage supply and an output node. The first voltage supply has a first voltage. The second set of transistors is connected between the output node and a second voltage supply. The second voltage supply has a second voltage. The first feedback transistor is connected to the output node, a first node and a second node. The second feedback transistor is connected to the output node, a third node and a fourth node. The first circuit is coupled to and configured to supply the second supply voltage to the second node. The second circuit is coupled to and configured to supply the first supply voltage to the fourth node.

Integrated circuit and method of manufacturing same

Growing community of inventors

Shanghai, China

Lei Pan