Globalfoundries Inc.

International Business Machines Corporation

Globalfoundries U.S. Inc.

Lei L Zhuang

Chiahsun Tseng

Lars W Liebmann

Jin Ping Liu

Ruilong Xie

Chun-chen Yeh

Balasubramanian Pranatharthiharan

Terence B Hook

Robert C Wong

Yunpeng Yin

Ananthan Raghunathan

Lawrence Alfred Clevenger

Jed Hickory Rankin

Fee Li Lie

Shreesh Narasimha

Guillaume Bouche

Stuart A Sieg

Dongbing Shao

Timothy A Brunner

Mahender Kumar

Xintuo Dai

Ahmed Hassan

Amr Y Abdo

In a self-aligned fin cut process for fabricating integrated circuits, a sacrificial gate or an epitaxially-formed source/drain region is used as an etch mask in conjunction with a fin cut etch step to remove unwanted portions of the fins. The process eliminates use of a lithographically-defined etch mask to cut the fins, which enables precise and accurate alignment of the fin cut.

Methods of performing fin cut etch processes for FinFET semiconductor devices

An extreme ultraviolet (EUV) mask including an absorber structure is disclosed. The absorber structure may include at least one slanted and/or concave sidewall. The absorber structure may include a sidewall including a step. A method of forming an absorber for an EUV mask is disclosed. The method may include etching an absorber layer using a mask to form an absorber structure having a sidewall wherein an outer edge of the top surface of the sidewall is closer to a central vertical axis of the absorber structure than an outer edge of the bottom surface of the sidewall. The method may include performing additional etching steps to form a step along the sidewall of the absorber structure. The etching may include combinations of anisotropic etching in different directions, and/or isotropic etching. The method may include etching an absorber layer including multiple absorber layers having different material properties on the ML reflector.

Extreme ultraviolet (EUV) mask absorber and method for forming the same

Fabrication method for a semiconductor memory device and structure are provided, which includes: providing at least two mask layers over a pair of fin structures extended above a substrate, wherein a first mask layer of the at least two mask layers is orthogonal to a second mask layer of the at least two mask layers; and patterning the pair of fin structures to define a pass-gate transistor, wherein the first mask layer facilitates removing of a portion of a first fin structure of the pair of fin structures to define a first pass-gate fin portion of the pass-gate transistor, and the second mask layer protects a second fin structure of the pair of fin structures to define a second pass-gate fin portion of the pass-gate transistor.

Stable and reliable FinFET SRAM with improved beta ratio

A first photoresist layer is patterned with a first pattern that includes an opening in a region between areas of two adjacent via holes to be formed. The opening in the first photoresist is transferred into a template layer to form a line trench therein. The lateral dimension of the trench is reduced by depositing a contiguous spacer layer that does not fill the trench completely. An etch-resistant material layer is conformally deposited and fills the trench, and is subsequently recessed to form an etch-resistant material portion filling the trench. A second photoresist layer is applied and patterned with a second pattern, which includes an opening that includes areas of two via holes and an area therebetween. A composite pattern of an intersection of the second pattern and the complement of the pattern of the etch-resistant material portion is transferred through the template layer.

Non-bridging contact via structures in proximity

Various embodiments include measurement structures and methods for measuring integrated circuit (IC) images. In some cases, a measurement structure for use in measuring an image of an IC, includes: a first section having a positive shift spacing pattern; a second section, on an opposite side of the measurement structure, having a negative shift spacing pattern; and a third section having a reference spacing pattern for calibrating a measurement from at least one of the first section or the second section.

Structure and method to measure focus-dependent pattern shift in integrated circuit imaging

A method includes providing a semiconductor structure having a substrate including a longitudinally extending plurality of fins formed thereon. A target layout pattern is determined, which overlays active areas devices disposed on the fins. The target layout pattern includes a first group of sections overlaying devices having more fins than adjacent devices and a second group of sections overlaying devices having less fins than adjacent devices. A first extended exposure pattern is patterned into the structure, and includes extensions that extend sections of the first group toward adjacent sections of the first group. A second extended exposure pattern is patterned into the structure, and includes extensions that extend sections of the second group toward adjacent sections of the second group. Portions of the first and second extended exposure patterns are combined to form a final pattern overlaying the same active areas as the target pattern.

Methods to control fin tip placement

Integrated circuit structures formed using methods herein include a layer, and a material-filled line in the layer. The material-filled line includes a first linear item and a second linear item separated by a separation area of the layer. The first linear item has a first line end where the first linear item contacts the separation area. The second linear item has a second line end where the second linear item contacts the separation area. The first line end and the second line end include line end openings (filled with a material) that increase critical dimension uniformity of the first line end and the second line end.

Integrated circuit line ends formed using additive processing

A stack of a first hard mask portion and a second hard mask portion is formed over a semiconductor material layer by anisotropically etching a stack, from bottom to top, of a first hard mask layer and a second hard mask layer. The first hard mask portion is laterally recessed by an isotropic etch. A dielectric material layer is conformally deposited and planarized. The dielectric material layer is etched employing an anisotropic etch that is selective to the first hard mask portion to form a dielectric material portion that laterally surrounds the first hard mask portion. After removal of the second and first hard mask portions, the semiconductor material layer is etched employing the dielectric material portion as an etch mask. Optionally, portions of the semiconductor material layer underneath the first and second hard mask portions can be undercut at a periphery.

Self-aligned trench over fin

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Ridgefield, CT, United States of America

Lei L Zhuang