Intel Corporation

Lei Jiang

Sadasivan Shankar

Jin Liu

Thomas Bramblett

Rafael Rios

Muhammad M Khellah

Paul B Fischer

Kelin J Kuhn

Seiyon Kim

Iqbal Rajwani

Anupama Ambardar Thaploo

Pascal Meinerzhagen

Daniel Pantuso

Stephen Kim

Edwin B Ramayya

Suphachai Chai Sutanthavibul

Surya Sasi Kiran Tallapragada

Daivik H Bhatt

Embodiments of the present disclosure describe techniques and configurations for integrated thermoelectric cooling. In one embodiment, a cooling assembly includes a semiconductor substrate, first circuitry disposed on the semiconductor substrate and configured to generate heat when in operation and second circuitry disposed on the semiconductor substrate and configured to remove the heat by thermoelectric cooling. Other embodiments may be described and/or claimed.

Integrated thermoelectric cooling

Some embodiments include apparatuses and methods using the apparatuses. One of the apparatuses includes a first power supply node, a second power supply node, transistors coupled in parallel between the first and second power supply nodes, and a controller to provide a first voltage, a second voltage, and a third voltage to gates of the transistors based on digital information. The first, second, and third voltages have different values based on values of the digital information.

Power switching circuitry including power-up control

An apparatus for polishing a wafer comprising a rotatable polishing pad having a center of rotation and a rinse delivery conduit positioned adjacent to the polishing pad and substantially in radial alignment with the center. The rinse delivery conduit includes a plurality of nozzles to dispense a rinsing liquid. In one embodiment, the plurality of nozzles are configured and positioned to generate a higher flow rate of the rinsing liquid at the end of the rinse delivery conduit proximate to the center than at the end of the rinse delivery conduit distal to the center. In another embodiment, the rinse delivery conduit has a proximal end which is substantially adjacent the center and the distal end which is approximately adjacent an outer periphery of the pad.

Rinse apparatus and method for wafer polisher

A method is provided for creating a polish pad. This may involve determining a design layout of a wafer. The design layout may include a distribution of metal line features on the wafer. A polish pad design may be created/determined based on the determined layer. The polish pad may have asperities having a width greater than a width of metal line features of the wafer.

Polishing pad design

An efficient TCAD tool to analyze the variation of topography and thickness of interconnects and components of integrated circuits introduced by multiple-layer chemical-mechanical planarization (CMP). Contact stress distribution is determined on all scales as a function of topography. A formulation is used relating the pad deformation and therefore stress directly to pattern topography ({d}), and the pad mechanical properties. The 3-dimensional stress and deformation field is described, along with representation of the statistical pad roughness and slurry thickness information. These process conditions are also functions of the surface topography and contact regimes. The stress-topography relationship is represented as [A]{P}={d}, where [A] is the influence coefficient matrix determined by the contact mechanics, and {P} and {d} represent local stress and topography on patterns. With given initial topography and slurry rate kinetics, the surface evolution at each time step of CMP can be traced iteratively to obtain post-CMP topography.

Minimization of microelectronic interconnect thickness variations

Growing community of inventors

Camas, WA, United States of America

Lei Jiang