University of California

Lei He

Rajit Gadh

Chi-Cheng Chu

Yiyu Shi

Ching-Yen Chung

Bingjun Xiao

Naifeng Jing

Siddhartha Mal

Shivanand Prabhu

Omar Sheikh

Ju-Yueh Lee

Zhe Feng

In-place resynthesis for static memory (SRAM) based Field Programmable Gate Arrays (FPGAs) toward reducing sensitivity to single event upsets (SEUs). Resynthesis and remapping are described which have a low overheard and improve FPGA designs without the need of rerouting LUTs of the FPGA. These methods include in-place reconfiguration (IPR), in-place X-filling (IPF), and in-place inversion (IPV), which reconfigure LUT functions only, and can be applied to any FPGA architecture. In addition, for FPGAs with a decomposable LUT architecture (e.g., dual-output LUTs) an in-place decomposition (IPD) method is described for remapping a LUT function into multiple smaller functions leveraging the unused outputs of the LUT, and making use of built-in hard macros in programmable-logic blocks (PLBs) such as carry chain or adder. Methods are applied in-place to mapped circuits before or after routing without affecting placement, routing, and design closure.

In-place resynthesis and remapping techniques for soft error mitigation in FPGA

An expert system manages a power grid wherein charging stations are connected to the power grid, with electric vehicles connected to the charging stations, whereby the expert system selectively backfills power from connected electric vehicles to the power grid through a grid tie inverter (if present) within the charging stations. In more traditional usage, the expert system allows for electric vehicle charging, coupled with user preferences as to charge time, charge cost, and charging station capabilities, without exceeding the power grid capacity at any point. A robust yet accurate state of charge (SOC) calculation method is also presented, whereby initially an open circuit voltage (OCV) based on sampled battery voltages and currents is calculated, and then the SOC is obtained based on a mapping between a previously measured reference OCV (ROCV) and SOC. The OCV-SOC calculation method accommodates likely any battery type with any current profile.

Smart electric vehicle (EV) charging and grid integration apparatus and methods

Field Programmable Logic Arrays (FPGAs) are described which utilize multiple power supply voltages to reduce both dynamic power and leakage power without sacrificing speed or substantially increasing device area. Power reduction mechanisms are described for numerous portions of the FPGA, including logic blocks, routing circuits, connection blocks, switch blocks, configuration memory cells, and so forth. Embodiments describe circuits and methods for implementing multiple supplies as sources of V, multiple voltage thresholding V, signal level translators, and power gating of circuitry to deactivate portions of the circuit which are inactive. The supply voltage levels can be fixed, or programmable. Methods are described for performing circuit CAD in the routing and assignment process on FPGAs, in particular for optimizing FPGA use having the power reduction circuits taught. Routing methods describe utilizing slack timing, power sensitivity, trace-based simulations, and other techniques to optimize circuit utilization on a multi VFPGA.

Low-power FPGA circuits and methods

Methods are described herein which consider both die-to-die and within-die variations in effective channel length, threshold voltage, and gate oxide thickness, based on first developing closed-form models of chip level FPGA leakage and timing variations. Execution times are significantly reduced using these methods in comparison to performing detailed evaluation. The teachings provide mean and standard deviation which were found to be within 3% from those computed by Monte Carlo simulation, while leakage and delay variations can be up to 3&#xd7; and 1.9&#xd7;, respectively. Analytical yield models are derived which consider both leakage and timing variations, and use such models to evaluate FPGA device and architecture in response to process variations. The teachings allow improved modeling of leakage and timing yields and thus co-optimization to improve yield rates.

FPGA circuits and methods considering process variations

Integrated circuit apparatus and methods are described for inserting multi-Vbuffers within an interconnection tree during routing toward minimization of power under a delay constraint. Insertion of level converters is not necessary within the routing trees of the interconnect tree despite the insertion of the multi-Vbuffers. Techniques are described for controlling the dramatic complexity increment due to simultaneous delay and power consideration and increased buffer choices. Overhead reduction techniques are taught including: sampling based techniques, prediction based pruning techniques (PSP) and (PMP), and escape grid reduction, each of which are directed to multi-Vbuffer insertion. The resultant integrated circuits are routed with substantial power reductions over conventional routing.

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Irvine, CA, United States of America

Lei He