Alpha Omega Semiconductor Inc.

Other

Leeshawn Luo

Anup Bhalla

Sik Lui

Yueh-Se Ho

Mike F Chang

Ming Sun

Kai Chieh Liu

Xiao Meng Zhang

Xiaotian Zhang

Yueh Se Ho

A power device package for containing, protecting and providing electrical contacts for a power transistor includes a top and bottom lead frames for directly no-bump attaching to the power transistor. The power transistor is attached to the bottom lead frame as a flip-chip with a source contact and a gate contact directly no-bumping attaching to the bottom lead frame. The power transistor has a bottom drain contact attaching to the top lead frame. The top lead frame further includes an extension for providing a bottom drain electrode substantially on a same side with the bottom lead frame. In a preferred embodiment, the power device package further includes a joint layer between device metal of source, gate or drain and top or bottom lead frame, through applying ultrasonic energy.

Methods and configuration for manufacturing flip chip contact (FCC) power package

This invention discloses a power device package for containing, protecting and providing electrical contacts for a power transistor. The power device package includes a top and bottom lead frames for directly no-bump attaching to the power transistor. The power transistor is attached to the bottom lead frame as a flip-chip with a source contact and a gate contact directly no-bumping attaching to the bottom lead frame. The power transistor has a bottom drain contact attaching to the top lead frame. The top lead frame further includes an extension for providing a bottom drain electrode substantially on a same side with the bottom lead frame. In a preferred embodiment, the power device package further includes a joint layer between device metal of source, gate or drain and top or bottom lead frame, through applying ultrasonic energy. In another embodiment, a layer of conductive epoxy or adhesive, a solder paste, a carbon paste, or other types of attachment agents for direct no-bumping attaching the power transistor to one of the top and bottom lead frames.

Flip chip contact (FCC) power package

A semiconductor integrated circuit package having a leadframe () that includes a leadframe pad () disposed under a die () and a bonding metal area () that is disposed over at least two adjacent sides of the die. The increase in the bonding metal area () increases the number of interconnections between the metal area () and the die () to reduce the electric resistance and inductance. Furthermore, the surface area of the external terminals radiating from the package's plastic body () is increased if not maximized so that heat can be dissipated quicker and external terminal resistances reduced. The integrated circuit is applicable for MOSFET devices and the bonding metal area () is used for the source terminal (). The bonding metal area may have a 'L' shape, a 'C' shape, a &#x201c;J&#x201d; shape, an &#x201c;I&#x201d; shape or any combination thereof.

Integrated circuit package for semiconductior devices with improved electric resistance and inductance

A semiconductor integrated circuit package having a leadframe () that includes a leadframe pad () disposed under a die () and a bonding metal area () that is disposed over at least two adjacent sides of the die. The increase in the bonding metal area () increases the number of interconnections between the metal area () and the die () to reduce the electric resistance and inductance. Furthermore, the surface area of the external terminals radiating from the package's plastic body () is increased if not maximized so that heat can be dissipated quicker and external terminal resistances reduced. The integrated circuit is applicable for MOSFET devices and the bonding metal area (101) is used for the source terminal (). The bonding metal area may have a 'L' shape, a 'C' shape, a &#x201c;J&#x201d; shape, an &#x201c;I&#x201d; shape or any combination thereof.

Integrated circuit package for semiconductor devices with improved electric resistance and inductance

A DFN semiconductor package includes a leadframe having a die bonding pad formed integrally with a drain lead, a gate lead and a source lead, a die coupled to the die bonding pad, a die source bonding area coupled to the source lead and a die gate bonding area coupled to the gate lead, and an encapsulant at least partially covering the die, drain lead, gate lead and source lead.

Dual flat non-leaded semiconductor package

A semiconductor package and method for making a semiconductor package are disclosed. The semiconductor package has a top surface and a mounting surface and includes a die, a conducting connecting material, a plating material and an insulating material. The die has a processed surface facing towards the mounting surface of the semiconductor package. Exposed metal connections are at the processed surface of the die. The conducting connecting material is disposed on the exposed metal connections. The plating material is in contact with the conducting connecting material. The insulating material is formed around the conducting connecting material, and the plating material extends to the exterior of the insulating material.

Method of making semiconductor package with plated connection

A semiconductor package includes a lead frame having a plurality of leads and a lead frame pad, the lead frame pad including a die coupled thereto, at least one of the plurality of leads having an external portion sloped upwards relative to a bottom surface of the package, metal connectors connecting the die to the plurality of leads, and a resin body encapsulating the die, metal connectors and at least a portion of the lead frame.

Inverted J-lead for power devices

Semiconductor package with plated connection

Integrated circuit package for semiconductor devices having a reduced leadframe pad and an increased bonding area

A semiconductor package including a relatively thick lead frame having a plurality of leads and a first lead frame pad, the first lead frame pad including a die coupled thereto, bonding wires connecting the die to the plurality of leads, the bonding wires being aluminum, and a resin body encapsulating the die, bonding wires and at least a portion of the lead frame.

Power semiconductor package

This invention discloses a method for configuring a power MOSFET package by packaging several paralleled and separated MOSFET chips in the assembly. The method further includes a step of connecting the gate pad on each of these MOSFET chips with a low-resistance gate bus. The package resistance and inductance are significantly reduced and switching speed and heat dissipation are substantially improved.

Growing community of inventors

Santa Clara, CA, United States of America

Leeshawn Luo