Intel Corporation

Leeor Peled

Joseph Nuzman

Youfeng Wu

Andrew J Herdrich

David J Sager

Koichi Yamada

Ron Gabor

Shlomo Raikin

Ian M Steiner

Tin-Fook Ngai

Ruchira Sasanka

Suresh Srinivas

Jayaram Bobba

Ho-Seop Kim

Omar M Shaikh

Howard Chen

Michael Prinke

Jason A Domer

David M Durham

Kshitij Arun Doshi

Ravi L Sahita

Mohan J Kumar

Baiju V Patel

Ravishankar Iyer

Michael Lemay

Sara S Baghsorkhi

Jr-Shian Tsai

James G Hermerding, Ii

Vadim Sukhomlinov

Alexander Bachmutsky

Mingqiu Sun

Jeffrey D Chamberlain

Jeffrey J Cook

Larisa Novakovsky

Eric Dahlen

Nilesh K Jain

Mohammad R Haghighat

Mingwei Zhang

Amin Firoozshahian

Yeluri Raghuram

Sudheer Nair

Dmitry Babokin

Krishna Bhuyan

Anil Rao

Hanna Alam

Avishai Wagner

Amir Leibovitz

Areg Melik-Adamyan

Refael Mizrahi

Harshad S Sane

Teck Joo Goh

Anup Mohan

Gilad Olswang

Moran Peri

Ido Karavany

Eylon Toledano

Jeffery J Cook

Ronen Laperdon

Hadas Beja

Michal Moran

Jonathan Beimel

Wenyong Huang

Embodiments of systems, apparatuses and methods provide enhanced function as a service (FaaS) to users, e.g., computer developers and cloud service providers (CSPs). A computing system configured to provide such enhanced FaaS service include one or more controls architectural subsystems, software and orchestration subsystems, network and storage subsystems, and security subsystems. The computing system executes functions in response to events triggered by the users in an execution environment provided by the architectural subsystems, which represent an abstraction of execution management and shield the users from the burden of managing the execution. The software and orchestration subsystems allocate computing resources for the function execution by intelligently spinning up and down containers for function code with decreased instantiation latency and increased execution scalability while maintaining secured execution. Furthermore, the computing system enables customers to pay only when their code gets executed with a granular billing down to millisecond increments.

Function as a service (FaaS) system enhancements

Disclosed Methods, Apparatus, and articles of manufacture to dynamically enable and/or disable prefetchers are disclosed. An example apparatus include an interface to access telemetry data, the telemetry data corresponding to a counter of a core in a central processing unit, the counter corresponding to a first phase of a workload executed at the central processing unit; a prefetcher state selector to select a prefetcher state for a subsequent phase based on the telemetry data; and the interface to instruct the core in the central processing unit to operate in the subsequent phase according to the prefetcher state.

Methods and apparatus to dynamically enable and/or disable prefetchers

A simultaneous multi-threading (SMT) processor core capable of thread-based biasing with respect to execution resources. The SMT processor includes priority controller circuitry to determine a thread priority value for each of a plurality of threads to be executed by the SMT processor core and to generate a priority vector comprising the thread priority value of each of the plurality of threads. The SMT processor further includes thread selector circuitry to make execution cycle assignments of a pipeline by assigning to each of the plurality of threads a portion of the pipeline's execution cycles based on each thread's priority value in the priority vector. The thread selector circuitry is further to select, from the plurality of threads, tasks to be processed by the pipeline based on the execution cycle assignments.

Apparatus, method, and system for ensuring quality of service for multi-threading processor cores

Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program into multiple parallel threads are described. In some embodiments, the systems and apparatuses execute a method of original code decomposition and/or generated thread execution.

Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program to multiple parallel threads

A processor includes a front end to decode instructions, an execution unit to execute instructions, multiple caches at different cache hierarchy levels, a pipelined prefetcher, and a retirement unit to retire instructions. The prefetcher includes circuitry to receive a demand request for data at a first address within a first line in a memory and, in response, to provide the data at the first address to the execution unit for consumption, to prefetch a second line at a first offset distance from the first line into a mid-level cache, and to prefetch a third line at a second offset distance from the second line into a last-level cache. The prefetcher includes circuitry to prefetch, in response to another demand request, the third line into the mid-level cache, and a fourth line into the last-level cache. The prefetcher enforces minimum or maximum offset distances between prefetched data streams.

Pipelined prefetcher for parallel advancement of multiple data streams

Growing community of inventors

Haifa, Israel

Leeor Peled