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Leendert Jan Van Den Berg

Duncan George Elliott

A level shifter circuit for integrated circuits has one or more inputs that operate in a first voltage domain, and a signal output that operates in a second voltage domain. In some embodiments, the level shifter circuit receives two complementary input signals. The level shifter uses cross-coupled PMOS transistors with drain-bulk breakdown voltage less than the gate-oxide breakdown voltage of high-voltage PMOS transistors to prevent gate-oxide breakdown caused by sub-threshold leakage of auxiliary high-voltage PMOS transistors in the off state. Permanent gate-oxide breakdown is prevented through non-permanent sub-nanoamp drain-bulk junction breakdown. The level shifter circuit has the advantages of small circuit size and low static power consumption.

Level shifter circuits for integrated circuits

A frequency synthesis phase-locked loop architecture using a regenerative sampling latch is described. The frequency divider typically employed in the feedback path of a frequency synthesis phase-locked loop is replaced by a regenerative sampling latch with a binary output. The regenerative sampling latch subsamples the frequency synthesizer output to produce a low-frequency aliased signal that can be processed further or directly used to lock the phase-locked loop. This architecture is referred to as an alias-locked loop. The relaxed constraints on the regenerative sampling latch make it possible to create high-speed frequency synthesizer phase-locked loops without the suffering the limitations imposed by traditional dividers connected directly to the oscillator output.

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Edmonton, Canada

Leendert Jan Van Den Berg