U.S. Philips Corporation

Anteryon Bv

Leendert De Bruin

Robertus D Verhaar

Josephus M Van Laarhoven

Trung Tri Doan

Arjen Gerben Van Der Sijde

Edwin Maria Wolterink

Anton Petrus Maria Van Arendonk

Gerardus Maria Dohmen

Anton P Van Arendonk

Erik Harold Groot

Malcolm K Grief

Aloysius Franciscus Maria Sander

Harald Godon

The invention relates to a camera device and a method for manufacturing such a device. The camera device comprises an image capturing element, a lens element for imaging an object at the image capturing element and a spacer means for maintaining a predetermined distance along the main optical axis though the lens and the image capturing element, and lens substrate for carrying the lens wherein the spacer means comprises an adhesive layer. This enables a mass manufacturing process wherein parts of the individual camera elements can be manufactured in manifold on different substrates, after which the different substrates are stacked, aligned and joined via adhesive layers. In the manufacturing process the different distances between the plates and the wafers are adjusted and maintained via the spacer means comprising the adhesive layers. From the stack individual camera devices are sawn out.

Camera device, method of manufacturing a camera device, wafer scale package

Electrical connection is provided to a device region (3,4) bounded by an insulating region (12a,12b,9) and adjacent one major surface (1a) of a semiconductor body (1) by applying a flowable organic material to form an organic layer (20) on the one major surface (1a), defining a masking layer (30) over the organic layer (20), etching the organic layer (20) selectively with respect to the underlying device and insulating regions through a window (31) in the masking layer (30) to form an opening (21) exposing a contact area (11) of the device region (3,4) and depositing electrically conductive material, for example tungsten, to form a conductive pillar (40) within the opening (21) in contact with the contact area (11). The organic layer (20) is then removed so as to expose the conductive pillar (40), a layer 50 of insulating material is provided over the pillar, the insulating layer is etched to expose a top surface of the pillar and electrically conductive material deposited to contact the pillar (40).

Method of producing conductive pillars in semiconductor device

A semiconductor body has a surface structure (10) with an insulating layer (11) through which is formed an opening (12) defining a side wall (13) of insulating material bounding an exposed surface area (14a) of a region (14). An activating layer (15) is provided on the exposed surface area (14a) and the side wall (13) of the opening (12), and electrically conductive material deposited on the activating layer (15) to form an electrically conductive region (16) in the opening (12). The activating layer is provided so that the material (15a) on the sidewall (13) has different composition from the material (15b) on the exposed surface area (14a) and is selectively etched to remove the material (15a) from the sidewall (13) of the opening (12) leaving only the activating layer portion (15b) on the surface area (14a) of the underlying region so that little or no deposition of the electrically conductive material occurs on the opening sidewall (13), thereby inhibiting sideways growth of the electrically conductive material and thus avoiding or at least reducing the possibility of voids being formed in the electrically conductive region.

Method of manufacturing a semiconductor device having conductive

Electrical connection to a device region (3,4) of a semiconductor device is formed by providing a semiconductor body (1) having adjacent one major surface (12) a device region (3,4) bounded by an insulating region (19a,19b,9), providing an activating layer (11) on the one major surface (12), applying a flowable material as a layer (13) of photosensitive resist, exposing and developing the resist to define an opening (14) over a contact area (12a) of the device region (3,4), and selectively plating electrically conductive material into the opening (14) to form a conductive pillar (15) in electrical contact with the contatct area (12a). The layer (13) of photosensitive resist is removed after formation of the conductive pillar (15) and a layer of insulating material is then provided to cover the conductive pillar (15) and the surface (12). The insulating layer is then etched to expose a top surface (15a) of the conductive pillar (15).

Selectively plating conductive pillars in manufacturing a semiconductor

A method of enabling electrical connection to a substructure (10) forming part of an electronic device, such as an integrated circuit, is described in which an aluminum-containing electrically conductive level (1) is provided on a surface (12) of the substructure (10), an insulating layer (2) is deposited so as to cover the aluminum-containing electrically conductive level (1), a photosensitive resist layer (3) is provided on the insulating layer and a plasma etching step is then used to etch away insulating material so as to expose an electrically conductive surface to enable electrical connection to be made to the level (1). The insulating material (2) may be etched through a window in the resist layer (3) so as to form a via (14) or the resist layer (3) and insulating material (2) may be etched uniformly to provide a planarized surface. In the method, a layer (4) of another conductive material which is free of aluminum is provided on the level (1) prior to covering the level (1) with insulating material (2) so that the plasma etching step exposes an electrically conductive surface (4a) of the layer (4) of the said other conductive material which thus acts to mask the level (1) to prevent catalytic reaction between the aluminum and constituents in the plasma.

Method of enabling electrical connection to a substructure forming part

A method of the kind consisting in that a contact is obtained with an active zone (11) carried by a semiconductor substrate (10) by means of conductive contact studs (18a) located in the contact openings (16c) of an isolating layer (12) and in that then a metallic configuration of interconnections (22) is formed establishing the conductive connection with the conductive contact studs (18a). A separation layer (13) is provided between the isolating layer (12) and the conductive layer (18), which can be eliminated selectively with respect to the isolating layer (12). Thus, the isolating layer (12) retains its original flatness and the conductive contact studs (18a) have an upper level (20) exceeding slightly the level (21) of the isolating layer (12), thus favoring the contact between these contact studs (18a) and the metallic configuration of interconnections (22). Application in microcircuits having a high integration density.

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Eindhoven, Netherlands

Leendert De Bruin