Intel Corporation

Tahoe Research, Ltd.

Leena K Puthiyedath

James B Crossland

Vivekananthan Sanjeepan

Herbert H Hum

Eric J DeHaemer

James R Vash

Brinda Ganesh

Adrian C Moga

Richard Lawrence Carlson

Ganesh Kumar

David Bubien

Scott J Erlanger

Michelle M Sebot

Gilbert A Neiger

Jason W Brandt

Blaise B Fanning

Eric R Delano

Vincent J Zimmer

Michael A Rothman

Raj K Ramanujan

Michael Mishaeli

Asit K Mallick

Toby Opferman

Atul A Khare

Nikhil Talpallikar

Jim Coke

Abinash K Barik

Chandan Apsangi

Robert Valentine

Mark Jay Charney

Glenn J Hinton

Martin Guy Dixon

Andrew V Anderson

Barnes Cooper

Francis X Mckeen

Jawad Basit Khan

Ravishankar Iyer

Raanan Sade

Steven M Bennett

Ernie F Brickell

Stephen Anthony Fischer

Joseph Nuzman

Russell Jerome Fenger

Gideon Gerzon

Li Zhao

Anil Aggarwal

Donald K Newell

Srihari Makineni

Rinat Rappoport

John G Holm

Randolph L Campbell

Eric R DeLano

Michael C Walz

Ningde Xie

Ramesh G Illikkal

Rahul Seth

Raicsh Parthasarathy

Qingda Lu

Tony Opferman

Ernie Brickwell

Embodiments of an invention related to compacted context state management are disclosed. In one embodiment, a processor includes instruction hardware and state management logic. The instruction hardware is to receive a first save instruction and a second save instruction. The state management logic is to, in response to the first save instruction, save context state in an un-compacted format in a first save area. The state management logic is also to, in response to the second save instruction, save a compaction mask and context state in a compacted format in a second save area and set a compacted-save indicator in the second save area. The state management logic is also to, in response to a single restore instruction, determine, based on the compacted-save indicator, whether to restore context from the un-compacted format in the first save area or from the compacted format in the second save area.

Compacted context state management

Implementations of using tiles for caching are detailed In some implementations, an instruction execution circuitry executes one or more instructions, a register state cache coupled to the instruction execution circuitry holds thread register state in a plurality of registers, and backing storage pointer storage stores a backing storage pointer, wherein the backing storage pointer is to reference a state backing storage area in external memory to store the thread register state stored in the register state cache.

Systems, methods, and apparatuses utilizing CPU storage with a memory reference

Examples may include techniques for persistent memory virtualization. Persistent memory maintained at one or more memory devices coupled with a host computing device may be allocated and assigned to a virtual machine (VM) hosted by the host computing device. The allocated persistent memory based on a file based virtual memory to be used by the VM. An extended page table (EPT) may be generated to map physical memory pages of the one or more memory devices to virtual logical blocks of the file based virtual memory. Elements of the VM then enumerate a presence of the assigned allocated persistent memory, create a virtual disk abstraction for the file based virtual memory and use the EPT to directly access the assigned allocated persistent memory.

Techniques for persistent memory virtualization

A processor of an aspect includes a plurality of logical processors each having one or more corresponding lower level caches. A shared higher level cache is shared by the plurality of logical processors. The shared higher level cache includes a distributed cache slice for each of the logical processors. The processor includes logic to direct an access that misses in one or more lower level caches of a corresponding logical processor to a subset of the distributed cache slices in a virtual cluster that corresponds to the logical processor. Other processors, methods, and systems are also disclosed.

Processors having virtually clustered cores and cache slices

Examples may include techniques for an all persistent memory file system. The techniques to include allocating physical memory pages of memory devices of a persistent memory platform coupled with a computing platform. The techniques to also include storing context or relocated files to persistent memory physical address spaces for the memory devices and mapping process virtual address spaces for a working set associated with one or more instantiations of a program by circuitry at the computing platform.

Techniques for an all persistent memory file system

A disclosed example method to suspend and resume a device includes: after detecting a low-power suspend mode request, determining a storage performance of the device to store suspend state data; based on the storage performance of the device, setting a suspend flag to indicate a low-power suspend mode to a processor platform; when resuming from the low-power suspend mode, confirming a setting of a resume flag from the processor platform, the resume flag to notify an operating system to resume from the low-power suspend mode; and when the resume flag is set, restoring state data corresponding to an operating system context from a non-volatile dual-purpose system and storage memory.

Methods and apparatus to suspend and resume computing systems

A non-volatile random access memory (NVRAM) is used in a computer system to perform multiple roles in a platform storage hierarchy, specifically, to replace traditional mass storage that is accessible by an I/O. The computer system includes a processor to execute software and a memory coupled to the processor. At least a portion of the memory comprises a non-volatile random access memory (NVRAM) that is byte-rewritable and byte-erasable by the processor. The system further comprises a memory controller coupled to the NVRAM to perform a memory access operation to access the NVRAM in response to a request from the software for access to a mass storage.

System for configuring partitions within non-volatile random access memory (NVRAM) as a replacement for traditional mass storage

A non-volatile random access memory (NVRAM) is used in a computer system to provide instant responses to sleep state transitions. The computer system includes a processor coupled to an NVRAM, which is accessible by the processor without passing through an I/O subsystem. The NVRAM is byte-rewritable and byte-erasable by the processor. In response to a request to enter a powered sleep state, the computer system converts the powered sleep state into a powered-off sleep state with system memory context stored in the NVRAM. The powered sleep state is defined as a state in which power is supplied to volatile random access memory in the computer system, and the powered-off sleep state is defined as a state in which power is removed from the volatile random access memory. In response to a wake event, the computer system resumes working state operations using the system memory context stored in the NVRAM.

Method and system for providing instant responses to sleep state transitions with non-volatile random access memory

Apparatus for configuring partitions within phase change memory of tablet computer with integrated memory controller emulating mass storage to storage driver based on request from software

Various embodiments are generally directed to an apparatus, method and other techniques for initiating a transition into a lower power state, determining that a device process prevents a platform processing device from completing the transition to the lower power state and interrupting a processing component from an intermediate power state in order to process the process prior to execution of a defined event.

Techniques for entering a low power state

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Beaverton, OR, United States of America

Leena K Puthiyedath