National Science Council

Lee-Yuang Huang

Chorng-Kuang Wang

Chau-Chin Su

Jin-Jyh Lee

A sampling timing recovering circuit free from being troubled by a frequency error is provided. Such recovering circuit includes a phase locking circuit having a local frequency for processing an incoming signal having a phase, a specific parameter and an input symbol rate and for locking the phase of the incoming signal, and a frequency locking circuit electrically connected to the phase locking circuit for locking the input symbol rate of the incoming signal to enable the phase locking circuit to desiredly process the incoming signal. A method to this effect is also provided and includes the steps of a) processing an incoming signal having a phase, a specific parameter and an input symbol rate to have the phase lockable, b) locking the phase of the incoming signal, and c) locking the input symbol rate of the incoming signal to enable the incoming signal to be predeterminedly processed.

Growing community of inventors

Taoyuan Hsien, Taiwan

Lee-Yuang Huang