Sperry Corporation

Unisys Corporation

Sperry Rand Corporation

Lee T Thorsrud

Donald B Bennett

Thomas W Petschauer

Gary A Spencer

A bus error detection system is used to detect binary bus error signals. The bus lines include an odd parity line and an even parity line. A clock means provides at least two clock signal phases. An activatable driver drives both of the odd and the even parity lines to the same predefined logic level each time a first clock signal phase occurs. A parity checker coupled to the drive checks during a second clock signal phase the parity of the binary signals which appeared on said bus lines during a preceding first clock signal phase. The driver then drives either the odd or the even parity lines to a predefined logic state according to the parity determined by the parity checker during the second clock signal phase. A verification circuit verifies that only one of the odd and the even parity lines has been driven to a predefined logic state during said second clock phase, and that of both the odd and the even parity lines have been driven during said first clock signal phase to the same predefined logic level.

Bus error detection employing parity verification

A bus arbitration system comprising a plurality of bus lines and a clock which produces first and second phrases in which a drive generates a first logic state during the first phase to precharge the capacitance associated with the bus lines and generates either first or second logic state during the second phase. Also, a bus interface is described in which different types of information are transmitted during different phases.

Versatile interconnection bus

Bidirectional communication upon a high performance synchronous (25 MHz line transfer rate) parallel digital communication bus interconnecting large numbers (up to 256 along 1 meter of bus) of very large scale integrated (VLSI) cirucit devices is supported by VLSI wired-Or driver/receiver (D/R) circuit elements synergistically operative under a two-time-phase bus electrical protocol for bus drive. During a first phase of approximately 10 nanoseconds all interfacing driver circuits additively drive, or pull-up, connected bus lines to a +3 v.d.c. logical High condition. During a second phase of approximately 20 nanoseconds during each 40 nanosecond cycle time D/R circuits present high impedance to charged bus lines for maintenance of such logical High and transmission of a logical '0', or else one or more D/R circuits drain line charge toward 0 v.d.c. for transmission for a logical '1'. Two point driver to receiver, wired-OR, broadcast, and/or eavesdrop communication are supported for bus lines.

VLSI Wired-OR driver/receiver circuit

Each of the exclusive OR (XOR, or odd parity) and exclusive NOR (XNOR, or even parity) logical functions as between two signals input in both normal and inverted form is generated from separate logic circuits of two transfer gates implemented in complementary metal oxide semiconductor (CMOS) very large scale integrated circuit (VLSIC) technology. Replications of paired such XOR and XNOR logical circuits within a parity tree allow parity generation/detection as between 2.sup.N signals input in both normal and inverted form in only N propagation stages of typically average 0.9 nanosecond delay each stage when implemented in 11/4 micron feature size CMOS VLSIC.

Parity generation/detection logic circuit from transfer gates

Apparatus for scaling addresses received by a memory module in a modular requestor-memory system in which standard memory modules may be of a discretely variable size and utilized in a plurality of positions in an overall contiguous memory addressing scheme. In particular, this scaling apparatus enables a modular memory which is only partially populated, i.e., only able to respond to a subset of the set of all addresses available, to be located in any one of several positions representing different addressing ranges. This is accomplished without modification of the memory module itself. The memory module knows its discrete capacity, or size, by virtue of the population of the memory array storage locations (array cards) contained therein. The memory module then uses this information to scale, or strip off, the appropriate number of bits from the gross address to allow addressing of the restricted number of memory locations present in the memory module.

Apparatus for scaling memory addresses

An apparatus for enabling a central processing unit (CPU) to directly read the address transferred to a memory module to permit the CPU to test the address circuitry of the memory module without actually referencing an addressable location of the memory array within the memory module. A status register located within the memory module has two bit positions assigned to controlling the closed loop address capability. If the two assigned bit positions contain binary zeroes, the memory module operates normally by using each address received to address one addressable location of the memory array of the memory module. If one of the assigned bit positions contains a binary one, subsequent read commands cause the memory not to access the memory arrays but to return the portion of the address corresponding to the bit position containing the binary one (i.e., one bit position causes part of the address to be returned whereas the other bit position causes the remainder of the address to be returned) to the requesting CPU as if it were data read from the contents of the specified addressable location, thus permitting the CPU to directly verify the correct operation of the addressing circuitry of the memory module. Since the assigned bit positions of the status register may be easily altered under software control, the closed loop address capability may be rapidly and automatically invoked to periodically verify the correct operation of the addressing circuitry of the memory module.

Closed loop address

Apparatus for providing a closed loop data path within a memory module to enable a central processing unit (CPU) to test the error correction circuitry of the memory module under software control without the necessity of accessing the memory arrays within the memory module. The memory module has error correction circuitry providing single bit correction/double bit detection. The error correction circuitry generates an error code which is appended to each data word upon being written into the memory array of the memory module. The error correction circuitry uses the error code to detect and correct errors in each data word read from the memory array of the memory module. A status register within the memory module stores control and status information for communication between the central processing unit and the memory module. Two bit positions of the status register are dedicated to closed loop error correct. If both bit positions contain binary zeroes, the memory module operates normally. If one of the bit positions contains a binary one, a read or write command to the memory module causes a read from or write into temporary storage of the error code within the error correction circuitry. If the other bit position contains a binary one, a read or write command to the memory module causes a read from or write into temporary storage of the memory module rather than a read into or write from the memory array of the memory module. Using the capability to read from and write into the temporary storage of the memory module, a CPU may directly test the error correction circuitry under software control without reading from and writing into the memory array of the memory module.

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Saint Paul, MN, United States of America

Lee T Thorsrud