Hewlett-packard Company

Lee O Fleming

John Stephen Walther

Ross V La Fetra

This invention improves and simplifies prior art systems for automatic test generation methodologies. In this invention, combinational logic is used to prevent opposing tristate bus drivers from simultaneously providing a logic signal on a common bus during testing of an integrated circuit. The combinational logic also ensures that at most one tristate buffer is enabled at all times during testing to ensure the common bus is at either a full logical 1, logical 0, or non-driven state. By preventing opposing drive signals being applied to the common bus and thus ensuring the bus is at a full logical 1 or logical 0 state when driven, automatic test generation programs can accurately generate test vectors for the integrated circuit.

Local tristate control circuit

An improved integrated circuit chip design which is better adapted to testing using existing circuit testers is disclosed. The chip includes a parallel load instruction which reduces the number of words of tester memory needed to load the internal scan registers. The parallel load instruction loads memory cells connected to the input pins of the chip which are then shifted into the scan registers.

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Fremont, CA, United States of America

Lee O Fleming