Xilinx, Inc.

Lee Ni Chung

Randy J Simmons

Shahin Toutounchi

Arnold Y Louie

Teymour M Mansour

Tassanee Payakapan

Felino E Pagaduan

Jian Jun Shi

Tony Le

Srinivasa R Parthasarathy

Julian Lupu

Dahshi Shen

Shivani C Desai

Embodiments herein describe techniques for binning integrated circuits (ICs) using an adaptive binning system that can re-bin the ICs in response to receiving a new or updated test specification. Unlike static binning systems, in one embodiment, the binning system receives measured test data from a testing system. Put differently, instead of a testing apparatus simply indicating whether an IC does (or does not) satisfy the criteria in the test specification, the testing apparatus provides measured test data to the binning system. The binning apparatus can then store the received test data. As such, if a new test specification is received or generated, the binning system can use the already saved test data to re-bin the ICs using the criteria in the new test specification without having to re-test the ICs. In this manner, the binning system can re-categorize the ICs as customer needs or customer demand changes.

Flexible manufacturing flow enabled by adaptive binning system

In one embodiment, a configuration data sequence is input to a master programmable integrated circuit (IC). In response to control bits in the configuration data sequence, the master programmable IC transmits the configuration data sequence to one or more slave programmable ICs. The master programmable IC and the one or more slave programmable ICs are configured in parallel with configuration bits from the configuration data sequence.

Configuration and testing of multiple-die integrated circuits

Operation of an internal voltage supply level (Vgg) of an IC is characterized over operating temperature or at a selected temperature to determine a temperature-equivalent internal voltage level. The internal voltage supply of the IC is set to the temperature-equivalent level, and the IC is tested at room temperature to screen for low-temperature defects or high-temperature defects.

Internal voltage level shifting for screening cold or hot temperature defects using room temperature testing

A Built-in Self Test (BIST) system is provided in a Field Programmable Gate Array (FPGA) that can adjust test signal patterns provided for testing after partial reconfiguration of the FPGA. The BIST system includes a decoder that monitors I/O signals and provides an output indicating when I/O signals change indicating partial reconfiguration has occurred. The decoder output is provided to a BIST test signal generator providing signals to an IP core of the FPGA as well as a BIST comparator for monitoring test results to change test signals depending on the partial configuration mode.

Built-in self test (BIST) technology for testing field programmable gate arrays (FPGAs) using partial reconfiguration

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San Jose, CA, United States of America

Lee Ni Chung