Texas Instruments Corporation

Other

United States of America As Represented by the Secretary of the Air Force

Lee M Loewenstein

Cecil J Davis

Rhett B Jucha

Robert T Matthews

Randall C Hildenbrand

John I Jones

Joseph D Luttmer

Rudy L York

Dean W Freeman

Steve S Huang

Monte A Douglas

Keith Alan Joyner

James G Bohlman

James B Burris

Joseph V Abernathy

Bruce Simpson

Paul Mertens

Patricia Beauregard Smith

Ming J Hwang

Thomas E Tang

Douglas A Webb

Cesar M Garza

William Wesley Dostalik

Jiann Liu

Wayne G Fisher

Jeffrey Allen Hanson

Guy Vereecke

Rachelle J Bienstock

Jeff D Achenbach

Timothy A Wooldridge

John D Lawrence

Tom Tang

Joe V Abernathy

A method of manufacturing a semiconductor device includes placing a sample of a liquid chemical containing a contaminant on a substantially impurity-free surface of a substrate. The liquid chemical is evaporated, leaving the contaminant on the surface. The contaminant is concentrated in a scanning solution, which is then evaporated to form a residue. A concentration of the contaminant in the residue is determined.

Method for measuring contamination in liquids at PPQ levels

Chemical solution and method for reducing the metal contamination on the surface of a semiconductor substrate

An isolation structure is provided that includes a substrate (,), a refill material such as a refill oxide (,), a gate dielectric such as a gate oxide layer (,), and a gate conductor layer such a polysilicon gate layer (,). The substrate (,) has an active region (,), an active region (,), and a trench region provided between the active region (,) and the active region (,). The active region (,) includes a top corner (,) that is provided where an upper surface of the active region (,) and the trench wall of the trench region that is adjacent to the active region (,) meet. The refill oxide (,) is positioned within the trench region and extends to cover at least a portion of the top corner. The gate oxide layer (,) is provided on the upper surface of the active region (,). The polysilicon gate layer (,) is provided on an upper surface of the gate oxide layer (,).

Isolation structure and method

An isolation structure is provided that includes a substrate (10), a refill material such as a refill oxide (22), a gate dielectric such as a gate oxide layer (24), and a gate conductor layer such a polysilicon gate layer (26). The substrate (10) has an active region (12), an active region (14), and a trench region provided between the active region (12) and the active region (14). The active region (14) includes a top corner (32) that is provided where an upper surface of the active region (14) and the trench wall of the trench region that is adjacent to the active region (14) meet. The refill oxide (22) is positioned within the trench region and extends to cover at least a portion of the top corner. The gate oxide layer (24) is provided on the upper surface of the active region (14). The polysilicon gate layer (26) is provided on an upper surface of the gate oxide layer (24).

Trench isolation of a CMOS structure

A dry etch process for stripping LOCOS nitride masks (302) with fluorine based removal of oxynitride (312) followed by fluorine plus chlorine based removal of nitride (302) and any silicon buffer layer (303) without removal of pad oxide (304).

Isotropic polysilicon plus nitride stripping

Isotropic nitride stripping

Semiconductor processing

In one embodiment this is a method of clamping semiconductor wafers for processing with the active face down. The method comprises: supporting a face down wafer 10 on an intermediate support 15; placing a clamping surface 14 at least adjacent to a backside of the wafer; moving at least three bevel-edged pins 11 upward to engage the beveled edges 12 with portions of the periphery of the face to press the wafer 10 against the clamping surface 14; moving the intermediate support 15 away from the wafer 10, and removing photoresist from the wafer by ashing the photoresist, whereby photoresist is essentially completely removed and essentially no unremoved photoresist remains to contaminate later processing.

Wafer clamping method

A remote microwave plasma generator comprises the combination of two parts, a tunable microwave applicator, and a double wall, water cooled quartz/sapphire tube. The tunable waveguide applicator is a nonconducting adjustable waveguide short with a quartz/sapphire tube inserted through it. The adjustable end is one quarter of a guide wavelength from the center line of the tube, and the other side is 0.1 inches less in distance, thus permitting the applicator to be used with a triple stub tuner for optimum coupling.

Low particulate reliability enhanced remote microwave plasma discharge

A processing apparatus and method wherein a wafer is exposed to activated species generated by a first plasma which is separate from the wafer, but is in the process gas flow stream upstream of the wafer, and is also exposed to plasma bombardment generated by a second plasma which has a dark space which substantially adjoins the surface of the wafer. The in situ plasma is relatively low-power, so that the remote plasma can generate activated species, and therefore the in situ plasma power level can be adjusted to optimize the plasma bombardment. Ultraviolet light to illuminate the face of a wafer being processed is generated by a plasma which is within the vacuum chamber but is remote from the face of the wafer. It is useful to design the gas flow system such that the ultraviolet-generating plasma has its own gas feed, and the reaction products from the ultraviolet-generating plasma do not substantially flow or diffuse to the wafer face. A transparent isolator is usefully included between the ultraviolet plasma space and the processing space near the wafer face, so that the ultraviolet plasma can be operated at a vacuum level slightly different from that used near the wafer face, delete but this transparent window is not made thick enough to act as a full vacuum seal.

Processing method using both a remotely generated plasma and an in-situ

A processing apparatus and method wherein a wafer is exposed to activated species generated by a first plasma which is separate from the wafer, but is in the process gas flow stream upstream of the wafer, and is also exposed to plasma bombardment generated by a second plasma which has a dark space which substantially adjoins the surface of the wafer. The in situ plasma is relatively low-power, so that the remote plasma can generate activated species, and therefore the in situ plasma power level can be adjusted to optimize the plasma bombardment. Ultraviolet light to illuminate the face of a wafer being processed is generated by a plasma which is within the vacuum chamber but is remote from the face of the wafer and controlled independent of the in situ plasma. It is useful to design the gas flow system such that the ultraviolet-generating plasma has its own gas feed, and the reaction products from the ultraviolet-generating plasma do not substantially flow or diffuse to the wafer face. A transparent isolator is usefully included between the ultraviolet plasma space and the processing space near the wafer face, so that the ultraviolet plasma can be operated at a vacuum level slightly different from that used near the wafer face.

Wafer processing apparatus having independently controllable energy

A method and apparatus for sensing radiation 26 indicative of at least one process variable in a semiconductor process chamber 10 in which a reactant gas reacts to effect changes in a silicon wafer 12. The method comprises positioning a substantially transparent window 22 in a conduit 14 leading to the wafer 12 and then flowing the reactant gas in the conduit 14 past the window 22 and toward the wafer 12. The radiation 26 is then sensed through the window 22. In the preferred embodiment the window 22 is positioned with an optical path along the center axis of the conduit 14. Other systems and methods are also disclosed.

Method and apparatus for integrating optical sensor into processor

A system for measuring the temperature of a semiconductor wafer 12 comprises a light source 14, a photodetector 20 which is operable to determine light intensity, and a mirror 18 in a predetermined fixed position from a beam splitter 16. The components are positioned such that light from the light source 14 impinges the beam splitter 16 and subsequently reflects off the mirror 18 and the wafer 12 and is received by the photodetector 20. Changes in the temperature of the wafer 12 are calculated based upon changes in the intensity of the received light which depends upon the expansion/contraction of the wafer. The absolute temperature may be calculated based on a known reference temperature and the changes in wafer 12 temperature. A second system and method for measuring the temperature of a semiconductor wafer which includes the use of a plurality of mirrors and two beam splitters is also disclosed.

Semiconductor wafer temperature measurement system and method

An apparatus and method for the etching of semiconductor materials (14) is disclosed. The apparatus (10) includes a process chamber (12) having a remote generator (16) in fluid communication with the process chamber (12) for converting a noble gas (34) to a metastable gas (36). An etchant gas (40) is subsequently brought into the chamber (12) adjacent to the material (14), to mix and react with the metastable gas (36) at activation zone (38). The metastable gas (36) collides with the etchant gas (40) to cause the mixture to selectively etch the material 14.

Method and apparatus for etching semiconductor materials

An apparatus and a method for the etching of semiconductor materials is disclosed. The apparatus includes a process chamber which includes a plasma generator remote from and in fluid communication with the process chamber. The remote plasma generator includes an inlet tube, a discharge tube in fluid communication with the inlet tube, an excitation cavity surrounding the discharge tube, an outlet tube in fluid communication with the discharge tube and a process chamber, and an injection tube in the outlet tube.

Method for etching semiconductor materials using a remote plasma

Growing community of inventors

Plano, TX, United States of America

Lee M Loewenstein