Sandisk Technologies Inc.

Western Digital Technologies, Inc.

Sandisk Corporation

Lee M Gavens

Jianmin Huang

Chris Avila

Jian Feng Chen

Sergey Anatolievich Gorobets

Chris Nga Yee Avila

Neil David Hutchinson

Meiqing He

Yingda Dong

Idan Alrod

Nian Niles Yang

Steven Theodore Sprouse

Gautam Ashok Dusija

Yoav Weinberg

Kulachet Tanpairoj

David Chaim Brief

Neil David Hutchison

Arun Thandapani

Charles Michael Schroter

Rakshit Tikoo

Yogendra Singh Sikarwar

Bhuvan Khurana

Sebastien Andre Jean

Ankit Vijay Naghate

Nagdi Tafish

Yinda Dong

Ashish Singla

Daniel Lee

Christopher Dinh

Ken Jianhui Hu

Shing Wong

Jian Chen

A memory device includes logic to detect the last page written in multi-plane non-volatile memory. The device includes a memory array, and a storage controller. The memory array includes multiple planes and multiple word lines operable on the memory array. The storage controller is configured to divide the word lines into contiguous sub-ranges and assign a subset of the word lines to boundaries of the sub-ranges. Each word line of the subset of word lines is assigned to a page in a different one of the memory planes. The controller operates the subset of word lines to sense a page programmed or erased state from each of the memory planes in parallel.

Detecting last page written in multi-plane non-volatile memory

An example of a system includes a plurality of non-volatile memory dies, a memory bus coupled to the plurality of non-volatile memory dies, and one or more control circuits coupled to the plurality of non-volatile memory dies through the memory bus. The one or more control circuits include a plurality of die-specific request queues configured in a one-to-one correspondence with the plurality of non-volatile memory dies. The one or more control circuits are configured to add die-specific atomic requests to individual die-specific request queues of the plurality of die-specific request queues independently of each other in response to die-specific triggering events.

Storage device with multi-die management

The present disclosure, in various embodiments, describes technologies and techniques for use by a data storage controller or similar device for efficiently and intelligently determining whether to use cached or non-cached memory access commands when accessing a non-volatile memory (NVM) device, such as a particular die of a multi-die NAND flash memory. In some examples, the data storage controller assesses the fill status of a particular memory access die queue (e.g., whether the queue is mostly full or mostly empty) and then determines whether to submit memory access commands to a NAND die as cached operations or non-cached operations based on the assessed fill status. In illustrative examples, the determination is made by a die manager based on the number of entries in the queue, with cached commands used if the entries exceed a predetermined threshold, and non-cached commands used otherwise. Method, system and apparatus examples are provided herein.

Controlling cached/non-cached memory access decisions based on memory access queue fill levels

A method of managing a memory bus includes identifying sub-operations required for execution of commands, maintaining a list of released sub-operations containing only released unexecuted sub-operations directed to individual dies that are identified as available, accessing the dies until the list is empty, subsequently, polling to identify dies that are available, and subsequently resuming accessing the dies by executing only sub-operations from the list until the list is empty.

Memory bus management

A system and method for using virtual physical addresses in a non-volatile memory device are disclosed. The physical layout of the non-volatile memory device may have physical die that are not a power-of-2 in number. In order to advantageously use the power-of-2 die number, which enables using a power-of-2 die interleave, a virtual physical addressing scheme is used. In particular, the virtual physical addressing scheme includes virtual die and virtual blocks, wherein the virtual die are a power-of-2 in number. Further, a conversion between the virtual physical addressing scheme and the actual physical addressing scheme is provided. In this way, for certain operations of the memory device, the virtual addressing scheme is used. For other operations, such as reading from, writing to or erasing, the actual physical addressing scheme is used.

Flash memory using virtual physical addresses

A data storage device that includes a controller and a non-volatile memory may perform a method that includes comparing, in the controller, first parameter values of a first group of parameter values to second parameter values of a second group of parameter values. The second parameter values of the second group of parameter values are associated with a scheduled non-volatile memory operation. The first parameter values correspond to parameter values that are in the non-volatile memory. The method includes sending, from the controller to the non-volatile memory, a parameter value of the second group in response to determining that the parameter value differs from a corresponding parameter value of the first group.

Devices and methods to conditionally send parameter values to non-volatile memory

Systems, methods, and apparatuses are provided to obtain diagnostic information from a storage device. A read command may be transmitted to a storage device, where the read command conforms to a block level storage protocol and is directed to an unused logical unit of storage memory included in the storage device, to an invalid logical block address, and/or to a mode page. The unused logical unit may be a predetermined logical unit of the storage memory that is not allocated by a file system. Diagnostic data may be received from the storage device in response to the read command. The diagnostic data may be information related to operation of the storage device and/or a component of the storage device.

Obtaining diagnostic information through host interfaces

In a nonvolatile memory array, such as a three-dimensional array of charge-storage memory cells, data is randomized so that data of different strings along the same bit line are randomized using different keys and portions of data along neighboring word lines are randomized using different keys. Keys may be rotated so that data of a particular word line is randomized according to different keys in different strings.

Data randomization in 3-D memory

A non-volatile memory chip having SLC blocks acting as a write cache for MLC blocks for high density storage requires constant copying or folding of SLC blocks into MLC blocks. To avoid the time-consuming toggling out and in of the pages of the entire SLC block for ECC checking by a controller chip, only a small sample is checked. An optimal read point for reading the memory cells in the sample of the SLC block is dynamically determined by trying different read points so that the data is read within an error budget. Once the optimal read point is determined, it is used to read the entire SLC block without further error checking. Then the SLC block can be copied (blind folded) to the MLC block with the confidence of being within the error budget.

Non-volatile memory and method having efficient on-chip block-copying with controlled error rate

Data errors in non-volatile memory inevitably increase with usage and with higher density of bits stored per cell. The memory is configured to have a first portion operating with less error but of lower density storage, and a second portion operating with a higher density but less robust storage. An error management provides reading and checking the copy after copying to the second portion. If the copy has excessive error bits, it is repeated in a different location either in the second or first portion. The reading and checking of the copy is accelerated by reading only a sample of it. The sample is selected from a subset of the copy having its own ECC and estimated to represent a worst error rate among the copy it is sampling. One embodiment has the sample taken from one bit of each multi-bit memory cell of a group.

Non-volatile memory and method with accelerated post-write read to manage errors

A memory system and methods of its operation are presented. The memory system includes a controller and a non-volatile memory circuit, where the non-volatile memory circuit has a first section, where data is stored in a binary format, and a second section, where data is stored in a multi-state format. The memory system receives data from the host and performs a binary write operation of the received data to the first section of the non-volatile memory circuit. The memory system subsequently folds portions of the data from the first section of the non-volatile memory to the second section of the non-volatile memory, wherein a folding operation includes reading the portions of the data from the first section rewriting it into the second section of the non-volatile memory using a multi-state programming operation. The controller determines to operate the memory system according to one of multiple modes. The modes include a first mode, where the binary write operations to the first section of the memory are interleaved with folding operations at a first rate, and a second mode, where the number of folding operations relative to the number of the binary write operations to the first section of the memory are performed at a higher than in the first mode. The memory system then operates according to determined mode. The memory system may also include a third mode, where folding operations are background operations executed when the memory system is not receiving data from the host.

Non-volatile memory with multi-gear control using on-chip folding of data

Data errors in non-volatile memory inevitably increase with usage and with higher density of bits stored per cell. The memory is configured to have a first portion operating with less error but of lower density storage, and a second portion operating with a higher density but less robust storage. Input data is written and staged in the first portion before being copied to the second portion. An error management provides checking the quality of the copied data for excessive error bits. The copying and checking are repeated on a different location in the second portion until either a predetermined quality is satisfied or the number or repeats exceeds a predetermined limit. The error management is not started when a memory is new with little or no errors, but started after the memory has aged to a predetermined amount as determined by the number of erase/program cycling its has experienced.

Non-volatile memory and method with post-write read and adaptive re-write to manage errors

This invention relates generally to methods and computer readable media for upgrading firmware stored in a non-volatile memory, in phases, and restoring firmware in-situ to compensate for failed firmware upgrades. In various embodiments, methods and computer readable media can upgrade and restore the firmware as the non-volatile memory remains functioning. In one embodiment, a method includes designating a first copy of firmware for accessing, and designating a second copy of the firmware for upgrading. The method continues by accessing one or more firmware instructions from the first copy. It also can include upgrading at least a portion of the second copy with at least a portion of new firmware. Upgrading the second copy can be coincident or substantially coincident to accessing the one or more firmware instructions in the first copy.

Methods and apparatus for performing resilient firmware upgrades to a functioning memory

A memory system and methods of its operation are presented. The memory system includes a volatile buffer memory and a non-volatile memory circuit, where the non-volatile memory circuit has a first section, where data is stored in a binary format, and a second section, where data is stored in a multi-state format. When writing data to the non-volatile memory, the data is received from a host, stored in the buffer memory, transferred from the buffer memory to into read/write registers of the non-volatile memory circuit, and then written from the read/write registers to the first section of the non-volatile memory circuit using a binary write operation. Portions of the data and then subsequently folded from the first section of the non-volatile memory to the second section of the non-volatile memory, where a folding operation includes reading the portions of the data from multiple locations in the first section into the read/write registers and performing a multi-state programming operation of the portions of the data from the read/write registers into a location the second section of the non-volatile memory. The multi-state programming operations include a first phase and a second phase and one or more of the binary write operations are performed between the phases of the multi-state programming operations.

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Milpitas, CA, United States of America

Lee M Gavens