Advanced Micro Devices Corporation

Lee-Lean Shu

Tai C Shyu

Patrick T Chuang

Tai-Ching Shyu

Chao-Ven Kao

A CMOS, midpoint sense amplification system for controlling the dynamics of the sense amplification phase of the sense cycle of a CMOS DRAM. The system includes a tracking circuit for initiating the first stage of the sense amplification phase when the differential voltage signal attains a first predetermined value. Circuitry for controlling the sense amplification rate and equalizing current supplied to the source nodes during the first stage is disclosed. In one embodiment, circuitry for detecting when the amplitude of the signal has increased to a second predetermined value and for increasing the sense amplification rate during the second and third stages of the sense amplification phase is disclosed.

Midpoint sense amplification scheme for a CMOS DRAM

A system for preventing forward biasing of the bit line junctions formed between the N-well and bit lines of a CMOS memory. The system includes a gating system for maintaining the bit line voltage at V.sub.CC /2 whenever the well voltage is less than V.sub.CC. A well regulator and well pump maintain the well voltage at a selected multiple of V.sub.CC.

CMOS N-well bias generator and gating system

A low power, low output impedance, CMOS voltage reference with high source/sink current driving capability. A CMOS current mirror preamplifier includes matched transistor pairs having their W/L ratios scaled to reduce the level of current to the subthreshold region. A CMOS source follower output stage also has its transistors biased in the subthreshold region. Circuitry for protecting the preamplifier from the effects of supply voltage and output voltage bumps is also disclosed.

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Milpitas, CA, United States of America

Lee-Lean Shu