Gsi Technology, Inc.

Sony Electronics Inc

Other

Giga Semiconductor, Inc.

Lee-Lean Shu

Chao-Hung Chang

Yoshinori Sato

Avidan Akerib

Patrick Chuang

Jyn-Bang Shyu

Jae Hyeong Kim

Kurt T Knorpp

Eli Ehrman

Mu-Hsiang Huang

Bob Haig

Katsunori Seno

Paul M-Bhor Chiang

Chenming W Tung

Stephen Lee

Robert Haig

Gi-Won Cha

Soon-Kyu Park

Tuan Duc Nguyen

William Le

Hsin You S Lee

Taiching Shyu

Park Soon-Kyu

A memory cell and processing array that has a plurality of memory are capable of performing logic functions, including an exclusive OR (XOR) or an exclusive NOR (XNOR) logic function. The memory cell may have a read port in which the digital data stored in the storage cell of the memory cell is isolated from the read bit line.

Computational memory cell and processing array device using the memory cells for XOR and XNOR computations

A storage array for computational memory cells formed as a memory/processing array provides storage of the data without using the more complicated computational memory cells for storage. The storage array may have multiple columns of the storage cells coupled to a column of the computational memory cells. The storage array may have ECC circuitry.

Storage array circuits and methods for computational memory cells

A processing array that performs one cycle full adder operations. The processing array may have different bit line read/write logic that permits different operations to be performed.

Processing array device that performs one cycle full adder operation and bit line read/write logic features

A memory cell that may be used for computation and processing array using the memory cell are capable to performing a logic operation including a boolean AND, a boolean OR, a boolean NAND or a boolean NOR. The memory cell may have a read port that has isolation circuits that isolate the data stored in the storage cell of the memory cell from the read bit line.

Computational memory cell and processing array device using memory cells

Computational memory cell and processing array device using complementary exclusive or memory cells

An ultra low VDD memory cell has a ratioless write port. In some embodiments, the VDD operation level can be as low as the threshold voltage of NMOS and PMOS transistors of the cell.

Ultra low VDD memory cell with ratioless write port

A computational memory cell and processing array have a ratioless write port so that a write to the memory cell does not need to overcome the drive strength of a PMOS transistor that is part of the storage cell of the memory cell. The computational memory cell also may have a second read port that has an isolation circuit.

Computational memory cell and processing array device with ratioless write port

Multi-bank, dual-pipe SRAM systems, methods, processes of operating such SRAMs, and/or methods of fabricating multi-bank, dual-pipe SRAM are disclosed. For example, one illustrative multi-bank, dual-pipe SRAM may comprise features for capturing read and write addresses, splitting and/or combining them via one or more splitting/combining processes, and/or bussing them to the SRAM memory banks, where they may be read and written to a particular bank. Illustrative multi-bank, dual-pipe SRAMs and methods herein may also comprise features for capturing two beats of write data, splitting and/or combining them via one or more splitting/combining processes, and bussing them to each SRAM bank, where they may be split/combined/recombined via one or more processes to write data to particular memory bank(s).

Systems and methods involving multi-bank, dual-pipe memory circuitry

Systems and methods of synchronous memories and synchronous memory operation are disclosed. According to one illustrative implementation, a memory device is disclosed comprising memory circuitry having a memory output, the memory circuitry including a sense amplifier having a first output and a second output, a first data path coupled to the first output of the sense amplifier, the first data path including 2 latches/registers, and a second data path coupled to the second output of the sense amplifier, the second data path including a plurality latches/registers. In further implementations, various control circuitry, connections and control signals may be utilized to operate the latches/registers in the first and second data paths according to specified configurations, control, modes, latency and/or timing domain information, to achieve, for example, pipelined output latching and/or double data rate output.

Systems and methods of pipelined output latching involving synchronous memory arrays

Growing community of inventors

Los Altos, CA, United States of America

Lee-Lean Shu