National Semiconductor Corporation

Analog Devices,inc.

Invensense, Inc.

Lee James Jacobson

Jiankang Bu

Andre Paul Labonte

Todd Wayne Karry

Thomas Chen

Sushil Bharatan

Jicheng Yang

Sergei Drizlikh

David Courtney Parker

Thomas Francis

Zualfquar Mohammed

Robert Maher

Andre′ Paul Labonte′

André Paul Labonté

Francis J McNally

A microphone system has a package with an interior chamber and an inlet aperture for receiving an acoustic signal, and a microphone die having a backplate and a diaphragm. The microphone is positioned within the package interior to form a front volume between the diaphragm and the inlet aperture. Accordingly, the microphone is positioned to form a back volume defined in part by the diaphragm within the interior chamber. The system also has a stop member positioned in the back volume so that the diaphragm is between the stop member and the backplate.

Microphone system with a stop member

A method of forming a variable pattern across a wafer using a reticle forms a plurality of first patterns on the wafer. The first pattern is repeated across the wafer and each first pattern has a first readable element. The method also forms a plurality of second patterns on the wafer. The second patterns is repeated across the wafer and each second pattern has a second readable element. The second patterns are positioned relative to the first patterns by aligning a first second pattern relative to one portion of a corresponding first pattern and then incrementally misaligning each successive second pattern in a row or a column relative to its corresponding first pattern. Thus, each corresponding first readable element and second readable element form a corresponding variable pattern.

Method of forming variable patterns using a reticle

A system and method is disclosed for providing a low voltage high density multi-bit storage flash memory. A dual bit memory cell of the invention comprises a substrate having a common source, a first drain and first channel, and a second drain and a second channel. A common control gate is located above the source. A first floating gate and a second floating gate are located on opposite sides of the control gate. Each floating gate is formed with a sharp tip adjacent to the control gate and an upper curved surface that follows a contour of the surface of the control gate. The sharp tips of the floating gates efficiently discharge electrons into the control gate when the memory cell is erased. The curved surfaces increase capacitor coupling between the control gate and the floating gates.

System and method for providing low voltage high density multi-bit storage flash memory

A method for creating graded or tapered dopant profiles in a semiconductor layer or layers. Preferably, a sub-micron horizontal tip feature is used to control the doping of the layer beneath the feature.

Method for forming a lens using sub-micron horizontal tip feature

A system and method is disclosed for providing contact etch selectivity for the etching of a plurality of contact etch holes through a dielectric layer of an integrated circuit. The method comprises the steps of obtaining a value of the reactive ion etch (RIE) lag for the dielectric layer, and selecting different values for the diameters of the contact etch holes based upon the desired depths of the contact etch holes and on the value of the RIE lag for the dielectric layer. The invention also comprises a contact diameter application processor that is capable of using RIE lag data to calculate contact diameters for contact etch holes for a mask design layout of an integrated circuit.

System and method for providing contact etch selectivity using RIE lag dependence on contact aspect ratio

A system and method is disclosed for testing integrated circuits that contain memory devices. A plurality of test circuits is created in which each test circuit incorporates a physical fault in a memory bit cell. Each of the test circuits generates a distinct electrical signature that is due to presence of the physical fault in the test circuit. The electrical signatures from the test circuits are compared with a signal from an integrated circuit memory device to determine whether any of the physical faults in the test circuits are present in the integrated circuit memory device.

System and method for providing testing and failure analysis of integrated circuit memory devices

A system and method is disclosed for providing a CMOS compatible single poly electrically erasable programmable read only memory (EEPROM) with memory cells that comprise an NMOS program transistor. In a first embodiment the memory cells of the EEPROM comprise a PMOS control capacitor. In a second embodiment the memory cells of the EEPROM comprise an NMOS control capacitor. A well bias voltage is applied to the NMOS program transistor instead of a gate bias voltage. The well bias voltage enables the injection of (1) channel hot electrons, (2) second hot electrons initiated by the channel hot electrons, and (3) drain impact ionization hot electrons into a floating gate of the NMOS program transistor.

System and method for providing a CMOS compatible single poly EEPROM with an NMOS program transistor

A single, controlled etch step can be used to form a sharp tip feature along a sidewall of an etch feature. An etch process is used that is selective to a layer of tip material relative to the substrate upon which the layer is deposited. A lag can be created in the etch, such that the etch rate is slower near the sidewall. The sharp tip feature is formed from the same layer of material used to create the etch feature. The sharp tip feature can be used to decrease the minimum critical dimension of an etch process, such as may be due to the minimum resolution of a photolithographic process. The novel tip feature also can be used for other applications, such as to create a microaperture for a photosensitive device, or to create a micromold that can be used to form objects such as microlenses.

Growing community of inventors

Cape Elizabeth, ME, United States of America

Lee James Jacobson