Au Optronics Corporation

Lee-Hsun Chang

Yu-Wen Lin

Kuei-Sheng Tseng

Yung-Tse Cheng

Wen-Pin Chen

Je-Hao Hsu

Tsung-Ting Tsai

Jing-Ru Chen

Chiu-Mei Yu

Shu-Fen Tsai

Chung-Lung Li

Ming-Chang Shih

Tung-Chang Tsai

Wei-Cheng Lin

Peng-Bo Xi

Ming-Sheng Lai

Chia-Yu Lee

Chu-Yu Liu

Tze-Chien Tsai

Hong-Shen Lin

Chih-Yu Peng

Chun-Ching Wei

Shyh-Feng Chen

Po-Jen Chiang

Chung-Jen Cheng Chiang

Tzu-Chin Huang

Wen-Bin Chen

Li-Fong Lin

Chun-Wei Wu

Shu-Wen Cheng

Bo-Ren Jiang

Chung-Jen Chen Chiang

A display panel includes a plurality of scan lines, a plurality of data lines, a plurality of power lines, a plurality of light emitting units, a plurality of first pixel circuits and a plurality of second pixel circuits. The plurality of light emitting units are arranged in an array and adapted to display different colors. In the organic light emitting units with the same color, some parts are connected to the first pixel circuits, and other parts are connected to the second pixel circuits. A first terminal and a second terminal of a first control transistor in the first pixel circuit are sequentially arranged on a forward direction of a first direction, and a first terminal and a second terminal of a second control transistor in the second pixel circuit are sequentially arranged on a reverse direction of the first direction.

Display panel

A multi-view stereoscopic display includes a display panel and a parallax barrier panel. The display panel includes a plurality of scan lines, a plurality of data lines, and a plurality of pixels. The parallax barrier panel includes a plurality of barriers and a plurality of control lines. The parallax barrier panel can block the display panel for displaying a plurality of images of different view angles. Each barrier corresponds to a predetermined number of pixels of the same data line. The barriers corresponding to the same scan line are divided into a plurality of groups of barriers. The plurality of control line corresponds to the plurality of scan lines. Each control line drives a group of barriers corresponding to the same scan line.

Multi-view stereoscopic display

An exemplary active matrix organic light emitting diode (OLED) display includes a data line, a current sensing line, a power line and a plurality of pixels all electrically coupled to the data line, the current sensing line and the power line. During a data current is writing to a selected one of the pixels, the selected pixel draws a current from the current sensing line, and the data line supplies a particular data voltage to the selected pixel according to the drawn current from the current sensing line until the drawn current matched with the data current; the other non-selected pixels draw currents from the power line for light-emission. Moreover, a pixel circuit and a data current writing method adapted for the above-mentioned active matrix OLED display also are provided.

Active matrix organic light emitting diode (OLED) display, pixel circuit and data current writing method thereof

An OLED display includes an OLED panel, two conducting wires and a power supply. A display region of the OLED panel is divided into two sub-display regions. The two conducting wires are both disposed on the panel and out of the display region, and first terminals of the two conducting wires are electrically coupled to pixels in the first sub-display region and the second sub-display region respectively. The length of a conducting wire is longer than that of another conducting wire so that the resistance of the conducting wire is larger than that of the said another conducting wire. The power supply provides a relatively high voltage and a relatively low voltage to the second terminals of the relatively long conducting wire and the relatively short conducting wire respectively, so that the voltages of the first terminals of the two conducting wires are substantially the same.

Organic light-emitting diode display

A display panel has a plurality of OLED pixels arranged in rows and columns. The pixel driving circuit has two or more current paths through a plurality of switching elements for providing the necessary current to the OLEDs in a pixel. The control end of each switching element is connected to the control end of the other switching elements, but each switching element has a separate power source which can be separately adjustable. In some embodiments, in a pixel or sub-pixel, one switching element is located at one end and one switching element is located at the other end of a pixel length, and each pixel is adjacent to a first power source line and a second power source line along the pixel length for separately providing the electrical power to two switching elements.

Pixel driving circuit with multiple current paths in a light emitting display panel

The present invention provides a display device, a displaying method thereof and a driving circuit for current-driven device. Each pixel of the display device includes a current-driven device and a driving circuit. A first terminal of the current-driven device is electrically coupled to a first preset voltage. The driving circuit includes a switch module and a capacitor. The switch module is electrically coupled to a data signal, a second terminal of the current-driven device and a second preset voltage. The switch module is for determining whether a current is allowed to flow through the current-driven device and setting a value of the current according to the data signal. The capacitor is electrically coupled between a periodically changed resetting signal and the switch module, to couple the resetting signal into the switch module to reset a voltage at a connection node between the capacitor and the switch module.

Display device and displaying method thereof, and driving circuit for current-driven device

A shift register of an LCD device operates based on two clock signals and maintains the gate voltage of an output transistor switch using two pull-down transistor switches. The gate voltages of the pull-down transistor switches are switched periodically between the high and low level of the clock signals. During the output period, the transistor switches have negative gate-source voltages so as to reduce leakage.

Shift register and a liquid crystal display device having the same

A gate driver on array of a display includes a substrate having a peripheral region, and a gate driver on array structure formed in the peripheral region. The gate driver on array structure includes a pull-down transistor, and the pull-down transistor has a gate electrode, an insulating layer, a semiconductor island, a source electrode, and a drain electrode. The semiconductor island extends out of both edges of the gate electrode, and extends out of an edge of the source electrode and an edge of the drain electrode.

Gate driver on array of a display

In a display device and a repairing method therefor, the display device includes a gate line and two gate-on-array circuits arranged at two sides thereof. Each of the gate-on-array circuits includes a stage coupled to the gate line. Each the stage includes a transistor and a repair circuit. The first source/drain electrode of the transistor is coupled to the gate line, and the second source/drain electrode of the transistor is coupled to receive a clock pulse signal. The repair circuit includes a first terminal coupled to the gate electrode of the transistor, a second terminal coupled to a predetermined potential, and at least one control terminal adapted to receive at least one repair signal to pull the potential on the gate electrode of the transistor to the predetermined potential. The transistor maintains at off-state when the at least one repair signal is supplied to the repair circuit.

Display device and repairing method therefor

A gate driving circuit having a low leakage current control mechanism is disclosed for providing a plurality of gate signals forwarded to a plurality of gate lines respectively. The gate driving circuit includes a plurality of shift registers. Each shift register includes a driving unit, an energy store unit, a buffer unit, a voltage regulation unit, and a control unit. The driving unit generates a gate signal based on a driving control voltage and a first clock. The buffer unit functions to receive a start pulse signal. The energy store unit provides the driving control voltage through performing a charging process based on the start pulse signal. The control unit generates a control signal based on the first clock and a second clock having a phase opposite to the first clock. The voltage regulation unit regulates the driving control voltage based on the control signal.

Gate driving circuit having a low leakage current control mechanism

A voltage pull-down circuit electrically connected between two scan lines and a bus line includes a transistor and an electrostatic discharge protection device. Each transistor comprises a source, a drain, and a gate electrically connected to one of the scan lines. Each gate is connected to another scan line, the source, and the drain through the electrostatic discharge protection device.

Voltage pull-down circuit

In a method of making device of a display, an insulating layer, a semiconductor layer, an ohmic contact layer, a second conductive layer, and a photoresist pattern are consecutively formed on a first conductive structure. The photoresist pattern includes a first thickness region, and a second thickness region outside the first thickness region. The thickness of the second thickness region is smaller than that of the first thickness region. In addition, in a gate driver on array (GOA) of a display, it includes a gate driver on array structure with a pull-down transistor. The pull-down transistor has a gate electrode, a semiconductor island, a source electrode and a drain electrode. The semiconductor island extends out of the edges of the gate electrode, the source electrode, and the drain electrode.

Method of making device of a display

A flat display structure including a substrate, a pixel matrix, a driving circuit and several voltage adapting devices and driving method thereof are provided. Each of voltage adapting devices includes an input terminal, a first control terminal and an output terminal. The input terminal is electrically connected to the i-th gate line Gcorresponding to the i-th pixel row R. The first control terminal is adapted to receive a first control signal. The output terminal is adapted to receive a working voltage.

Flat display structure and method for driving flat display

A control circuit includes a plurality of shift register stages. Each shift register stage is capable of outputting an individual output signal. The output signal is utilized to be a driving signal of next shift register stages. Each shift register stage comprises a transistor for receiving a clear signal CLR. The residual charges of the shift register stage can be released when the clear signal CLR is in a high voltage level. The clear signal CLR is enabled during a non-blanking time of a liquid crystal display (LCD). Each current register stage can use an output signal of another shift register stage which is apart from the current shift register stage by a predetermined interval as the clear signal CLR. The clear signal CLR is used to release the residual charges of the shift register stage before the shift register stage outputs its own output signal.

Control circuit for releasing residual charges

A shift register includes a plurality of stages cascade-connected with each other. Each stage includes a pull-up circuit, a pull-up driving circuit, and a pull-down circuit. The pull-up circuit coupled to a first clock signal is used for providing an output signal. The pull-up driving circuit includes a control circuit and a first transistor. The control circuit has a gate coupled to a previous stage, and a drain coupled to a second clock signal. The first transistor includes a gate coupled to the source of the control circuit, a drain coupled to a driving end of the previous stage, and a source coupled to a first input end. The pull-down circuit pulls down voltage on the first input end.

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Hsin-Chu, Taiwan

Lee-Hsun Chang