International Business Machines Corporation

Arm Limited

Motorola Corporation

Lee Evan Eisen

Hung Qui Le

Brian William Thompto

Jose Eduardo Moreira

Albert James Van Norstrand, Jr

Jentje Leenstra

Bruce Joseph Ronchetti

John Edward Derrick

Brian William Curran

Gregory William Alexander

Christian Jacobi

Brian David Barrick

Neil Burgess

Soummya Mallick

David Andrew Schroter

Michael Putrino

Daniel Arulraj

Eric M Schwarz

Michael Stephen Floyd

Avraham Ayzenfeld

Robert Thaddeus Golla

Gary Alan Gorman

Fadi Y Busaba

Balaram Sinharoy

Lisa Cranton Heller

Steven R Carlough

James Allan Kahle

Christopher Hans Olson

David S Levitan

Robert T Golla

Rajesh Bhikhubhai Patel

Brian R Konigsburg

Nigel John Stephens

Francis Patrick O'Connell

Tingdong Zhou

Graeme Peter Barnes

Marvin A Denman

Bryan P Black

Thomas Strach

John Wesley Ward, Iii

Huajun Wen

Alejandro Rico Carro

Albert J Loper, Jr

Russell A Reininger

Robert William Hay

Michael T Huffer

William John Starke

Alper Buyuktosunoglu

Pradip Bose

James Stephen Fields, Jr

Philip George Emma

Naresh Nayar

Richard James Eickemeyer

Paul Joseph Jordan

Bruce C Giamei

Kevin Franklin Reick

Cédric Denis Robert Airaud

Michael Filippo

David S Hutton

Belliappa Manavattira Kuttanna

Guillaume Bolbenes

Albin Pierrick Tonnerre

Andreas Bieswanger

Michael Billeci

Timothy A Elliott

Luca Nassi

John Barry Griswell, Jr

Robert Greg McDonald

Bradley David McCredie

Jesse Garrett Beu

Zhigang Hu

Rémi Marius Teyssier

Jelena Milanovic

Wolfram M Sauer

Douglas Robert Logan

Sung-Ho Park

Pasquale Ranone

Jaime Ferragut Martinez-Vara De Rey

An example design structure tangibly embodied in a machine readable medium includes a first arithmetic logic unit (ALU) to perform fixed point instructions using at least two general registers to read data from a first and second general register of a plurality of general registers and write a result in at least a third general register of the plurality of general registers. The design structure includes a second ALU to perform non-updating fixed point instructions using at least two general registers to only read data from the general registers. The design structure includes an efficiency logic unit coupled to the first ALU and the second ALU. The efficiency logic unit is to receive an instruction and determine whether the received instruction is an updating fixed point instruction or a non-updating fixed point instruction based on a number of general registers to be used to execute the received instruction.

Microprocessor including an efficiency logic unit

Data processing apparatus comprises processing circuitry to selectively apply vector processing operations to one or more data items of one or more data vectors each comprising an ordered plurality of data items at respective vector positions in the data vector, according to the state of respective predicate indicators associated with the vector positions; predicate generation circuitry to apply a processing operation to generate an ordered set of predicate indicators, each associated with a respective one of the vector positions, the ordered set of predicate indicators being associated with an ordered set of active indicators each having an active or an inactive state; and a detector to detect a status flag indicative of whether a predicate indicator at a position, in the ordered set of predicate indicators, corresponding to the position of an outermost active indicator having the active state, has a given state; in which the detector comprises: first and second circuitry to combine the ordered set of predicate indicators and the ordered set of active indicators using first and second respective logical bit-wise combinations to generate first and second ordered sets of intermediate data; and arithmetic circuitry to combine the first and second ordered sets of intermediate data using an arithmetic combination generating a carry bit, the detector generating the status flag in dependence upon the carry bit.

Data processing apparatus and method for generating a status flag using predicate indicators

Data processing apparatus comprises processing circuitry to apply processing operations to one or more data items of a linear array comprising a plurality, n, of data items at respective positions in the linear array, the processing circuitry being configured to access an array of n&#xd7;n storage locations, where n is an integer greater than one, the processing circuitry comprising: instruction decoder circuitry to decode program instructions; and instruction processing circuitry to execute instructions decoded by the instruction decoder circuitry; wherein the instruction decoder circuitry is responsive to an array access instruction, to control the instruction processing circuitry to access, as a linear array, a set of n storage locations arranged in an array direction selected, under control of the array access instruction, from a set of candidate array directions comprising at least a first array direction and a second array direction different to the first array direction.

Data processing

An in-order processor has a mapping storage element to store current register mapping information identifying, for each of two or more architectural register specifiers, which physical register specifies valid data for that architectural register specifier. At least one checkpoint storage element stores checkpoint register mapping corresponding to a checkpoint of previous architectural state. This enables checkpoints to be saved and restored simply by transferring mapping information between the mapping and checkpoint storage elements, rather than transferring the actual state data.

Checkpointing of architectural state for in order processing circuitry

Processing circuitry selectively applies vector processing operations to one or more data items of one or more data vectors. Each data vector comprises a plurality of data items at respective vector positions in the data vector according to the state of respective predicate indicators associated with the vector positions. Predicate generation circuitry apply a processing operation to generate a set of predicate indicators, each associated with a respective one of the vector positions, to generate a count value indicative of the number of predicate indicators in the set having a given state, and to store the generated set of predicate indicators and the count value in a predicate store.

Predicate indicator generation for vector processing operations

An apparatus and method are provided for comparing regions associated with first and second bounded pointers to determine whether the region defined for the second bounded pointer is a subset of the region defined for the first bounded pointer. Each bounded pointer has a pointer value and associated upper and lower limits identifying the memory region for that bounded pointer. The apparatus stores first and second bounded pointer representations, each representation comprising a pointer value having p bits, and identifying the upper and lower limits in a compressed form by identifying a lower limit mantissa of q bits, an upper limit mantissa of q bits and an exponent value e. A most significant p&#x2212;q&#x2212;e bits of the lower limit and the upper limit is derivable from the most significant p&#x2212;q&#x2212;e bits of the pointer value. Mapping circuitry is used to map the lower limit mantissas and upper limit mantissas of the first and second bounded pointer representations to a q+x bit address space comprising 2regions of size 2, where n1 is the value of n determined when using the exponent value of the first bounded pointer representation. Mantissa extension circuitry extends the lower limit and upper limit mantissas for each bounded pointer representation to create extended lower limit and upper limit mantissas comprising q+x bits, where a most significant x bits of each extended limit mantissa are mapping bits identifying which region the associated limit mantissa is mapped to. The determination circuitry then determines whether the region for the second pointer is a subset of the region for the first bounded pointer by comparing the extended lower and upper limit mantissas.

Apparatus and method for comparing regions associated with first and second bounded pointers

A processor core having multiple parallel instruction execution slices and coupled to multiple dispatch queues provides flexible and efficient use of internal resources. The configuration of the execution slices is selectable so that capabilities of the processor core can be adjusted according to execution requirements for the instruction streams. A plurality of load-store slices coupled to the execution slices provides access to a plurality of cache slices that partition the lowest level of cache memory among the load-store slices.

Reconfigurable processor with load-store slices supporting reorder and controlling access to cache slices

An apparatus and method of operating an apparatus are disclosed. The apparatus has a program counter permitted range storage element defining a permitted range of program counter values for the sequence of instructions it executes. Branch prediction circuitry predicts target instruction addresses for branch instructions. In response to a program counter modifying event, a program counter speculative range storage element is updated corresponding to each speculatively executed instruction after a branch instruction. Program counter permitted range verification circuitry is responsive to resolution of a modification of the program counter permitted range indication resulting from the program counter modifying event to determine whether the speculatively executed program counter range satisfies the permitted range of program counter values. A branch mis-prediction mechanism may support the response of the apparatus if the permitted range of program counter values is violated.

Handling modifications to permitted program counter ranges in a data processing apparatus

A processing pipeline has at least one front end stage for issuing micro-operations for execution in response to program instructions, and an execute stage for performing data processing in response to the micro-operations. At least one predicate register stores at least one predicate value. In response to a predicated vector instruction for triggering execution of two or more lanes of processing, the at least one front end stage issues at least one micro-operation to control the execute stage to mask an effect of a lane of processing indicated as disabled by a target predicate value. One of the front end stages may perform an early predicate lookup of the target predicate value to vary in dependence on the early predicate lookup, which micro-operations are issued to the execute store for a predicated vector instruction.

Early predicate look-up

An apparatus and method of operating a data processing apparatus are provided. The data processing circuitry is responsive to a hint instruction to then assert at least one performance modifying control signal, when subsequently generating control signals for other data processing instructions. This causes the data processing functional hardware which performs the data processing operations defined by the data processing instructions to operate in a modified manner, although the data processing results produced do not change in dependence on whether the at least one performance modifying control signal is asserted.

Hints in a data processing apparatus

Examples of techniques for designing processors are described herein. In one example, a design structure can be tangibly embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit. The design structure can include a logic to determine whether a received instruction is an updating fixed point instruction or a non-updating fixed point instruction. The design structure can include a first arithmetic logic unit (ALU) to execute the received instruction if the received instruction is determined to be an updating fixed point instruction and store an update value in a general register. The design structure can include a second arithmetic logic unit (ALU) to execute the received instruction if the received instruction is determined to be a non-updating fixed point instruction.

Structure for microprocessor including arithmetic logic units and an efficiency logic unit

A method in a computer-aided design system for generating a functional design model of a processor, is described herein. The method comprises generating a functional representation of logic to determine whether an instruction is an updating instruction or a non-updating instruction. The method further comprises generating a functional representation of a first arithmetic logic unit (ALU) coupled to a general register in the processor, the first ALU to execute the instruction if the instruction is an updating instruction and store an update value in the general register, and generating a functional representation of a second ALU in the processor to execute the instruction if the instruction is a non-updating instruction.

Generating design structure for microprocessor with arithmetic logic units and an efficiency logic unit

A data processing apparatus is provided, for performing a determination of whether a value falls within a boundary defined by a lower limit between 0 and 2and an upper limit between 0 and 2. The apparatus includes storage circuitry that stores each of the lower limit and the upper limit in a compressed form as a mantissa of q&#x3c;m bits and a shared exponent e. A most significant m-q-e bits of said lower limit and said upper limit are equal to a most significant m-q-e bits of said value. Adjustment circuitry performs adjustments to the lower limit and the upper limit in compressed form and boundary comparison circuitry performs the determination on the value using the lower limit and the upper limit in the compressed form.

Bounds checking

Circuitry comprises: a set of bit processing circuitries to apply two or more successive instances of bitwise processing to an ordered bit array; each bit processing circuitry for a given bit position within the ordered bit array comprising: bit shifting circuitry to selectively apply a bit shift of a respective input bit to a next bit processing circuitry in a first direction relative to the ordered bit array, in response to an active state of a bit shift control signal, the bit shifting circuitry not applying the bit shift in response to an inactive state of the bit shift control signal; and bit shift control circuitry to selectively allow or inhibit a bit shifting operation in response to one or more inhibit control signals; in which: the bit shift control circuitry is configured to selectively propagate an output inhibit control signal, indicating that a bit shifting operation should be inhibited, as an inhibit control signal to bit processing circuitry applying a next instance of the bitwise processing at the given bit position, in dependence upon the bit shift control signal and the one or more inhibit control signals.

Bit processing

A method of managing instruction execution for multiple instruction streams using a processor core having multiple parallel instruction execution slices. An event is detected indicating that either resource requirement or resource availability for a subsequent instruction of an instruction stream will not be met by the instruction execution slice currently executing the instruction stream. In response to detecting the event, dispatch of at least a portion of the subsequent instruction is made to another instruction execution slice. The event may be a compiler-inserted directive, may be an event detected by logic in the processor core, or may be determined by a thread sequencer. The instruction execution slices may be dynamically reconfigured as between single-instruction-multiple-data (SIMD) instruction execution, ordinary instruction execution, wide instruction execution. When an instruction execution slice is busy processing a current instruction for one of the streams, another slice can be selected to proceed with execution.

Processing of multiple instruction streams in a parallel slice processor

Growing community of inventors

Round Rock, TX, United States of America

Lee Evan Eisen