Future Wei Technologies, Inc.

Southern Methodist University

Yotta Networks, Inc.

Lee Dobson McFearin

Alan Gatherer

Sushma Wokhlu

Peter Yan

Fang Yu

Ashish Rai Shrivastava

Hao Luan

Tong Sun

Alex Elisa Chandra

Frederick Rush

Lakshman S Tamil

David W Matula

Bing Li

David F Wolf

Debashis Bhattacharya

Mark W Brown

Scott A Rothrock

Ywhpyng Harn

Gopalakrishnan Hari

Xiaotao Chen

Yan Bei

Alexander A Smith

Justin Hunt

Mitch Entezari

Xingfeng Chen

Earl Ponceti

Ke Ning

Chushun Huang

Glen Collier

Allesandro Fabbri

Quan Jiang

Joseph M McQuade

Peter-Michael Seidel

Technology for providing data to a processing unit is disclosed. A computer processor may be divided into a master processing unit and consumer processing units. The master processing unit at least partially decodes a machine instruction and determines whether data is needed to execute the machine instruction. The master processing unit sends a request to memory for the data. The request may indicate that the data is to be sent from the memory to a consumer processing unit. The data sent by the memory in response to the request may be stored in local read storage that is close to the consumer processing unit for fast access. The master processing unit may also provide the machine instruction to the consumer processing unit. The consumer processing unit may access the data from the local read storage and execute the machine instruction based on the accessed data.

Main processor prefetching operands for coprocessor operations

It is possible to reduce the latency attributable to memory protection in shared memory systems by performing access protection at a central Data Ownership Manager (DOM), rather than at distributed memory management units in the central processing unit (CPU) elements (CEs) responsible for parallel thread processing. In particular, the DOM may monitor read requests communicated over a data plane between the CEs and a memory controller, and perform access protection verification in parallel with the memory controller's generation of the data response. The DOM may be separate and distinct from both the CEs and the memory controller, and therefore may generally be able to make the access determination without interfering with data plane processing/generation of the read requests and data responses exchanged between the memory controller and the CEs.

System and method for shared memory ownership using context

Disclosed is method for operating an interposer that includes assigning a binary port weight to a plurality of input ports of the interposer. The sum of all of the port weights is less than or equal to a number of traversals available to the interposer in a cycle. A traversal counter is set zero at the beginning of each cycle. The output of the traversal counter is a binary number of m bits. A mask is generated when a bit of the traversal counter transitions from a zero to a one. The mask is generated having the m&#x2212;k+1 bit of the mask equal to one and all other bits of the mask equal to zero. Data is transmitted from each port when both the binary port weight and the mask have a one in the same bit position.

NoC interconnect with linearly-tunable QoS guarantees for real-time isolation

The present disclosure relates to a system and method of managing operation of a cache memory. The system and method assign each nested task a level, and each task within a nested level an instance. Using the assigned task levels and instances, the cache management module is able to determine which cache entries to evict from cache when space is needed, and which evicted cache entries to recover upon completion of preempting tasks.

Caching structure for nested preemption

Methods and apparatus for inter-process communication are provided. A circuit may have a plurality of clusters, and at least one cluster may have a computation element (CE), a memory operatively coupled with the CE, and an autonomic transport system (ATS) block operatively coupled with the CE and the memory. The ATS block may be configured to perform inter-process communication (IPC) for the at least one cluster. In one embodiment, the ATS block may transfer a message to a different cluster based on a request from the CE. In another embodiment, the ATS block may receive a message by allocating a buffer in the memory and write the message into the buffer. The ATS block may also be configured to manage synchronization and schedule tasks for the CE.

Scalable autonomic message-transport with synchronization

Systems and techniques for advance cache allocation are described. A described technique includes selecting a job from a plurality of jobs; selecting a processor core from a plurality of processor cores to execute the selected job; receiving a message which describes future memory accesses that will be generated by the selected job; generating a memory burst request based on the message; performing the memory burst request to load data from a memory to at least a dedicated portion of a cache, the cache corresponding to the selected processor core; and starting the selected job on the selected processor core. The technique can include performing an action indicated by a send message to write one or more values from another dedicated portion of the cache to the memory.

Advance cache allocator

Systems and methods for optical cross connects which switch data at a container (packet) level. In one embodiment, a plurality of optical switch edges are coupled to an optical switch core via a minimal number of optical fibers. The switch core is configured to optically switch data from an ingress edge to one of a plurality of egress edges in a nonblocking fashion. The ingress edge receives data streams and distributes the data among a plurality of container processors. Each of these container processors produces an optical signal of a different wavelength, which can then be multiplexed with others to form a multiple-wavelength optical signal that is transmitted to the switch core. The switch core then switches successive portions (containers) of the multiple-wavelength signal to the egress edges to which they are respectively destined. The respective egress edges perform the reverse of this process to form output data signals.

Container based crossconnect

A circuit and methodology for higher radix multiplication with improved partial product generation. The invention relates to the design of a high precision multiplier for an arithmetic unit of a digital processor.

Higher radix multiplier with simplified partial product generator

Growing community of inventors

Plano, TX, United States of America

Lee Dobson McFearin