Taiwan Semiconductor Manufacturing Comp. Ltd.

TSMC Nanjing Company, Limited

Lee-Chung Lu

Li-Chun Tien

Hui-Zhong Zhuang

Shang-Chih Hsieh

Chi-Lin Liu

Po-Hsiang Huang

Ting-Wei Chiang

Ta-Pen Guo

Sheng-Hsiung Chen

Yi-Kan Cheng

Yuan-Te Hou

Chung-Hsing Wang

Jerry Chang Jui Kao

Fong-yuan Chang

Jung-Chan Yang

Jerry Chang-Jui Kao

Huang-Yu Chen

Ru-Gun Liu

Yung-Chin Hou

Wei-Hsiang Ma

Chun-Chen Chen

Yung-Chen Chien

Chung-Te Lin

Fong-Yuan Chang

Ken-Hsien Hsieh

Cliff Hou

Chi-Yu Lu

Shyue-Shyh Lin

Chien-Ying Chen

Chang-Yu Wu

Wen-Hao Chen

Chin-Chou Liu

Ting Yu Chen

Chih-Liang Chen

Xiangdong Chen

Shun Li Chen

Gwan Sin Chang

Sang Hoo Dhong

Kuo-Nan Yang

Guo-Huei Wu

Hsiao-Shu Chao

Shao-Huan Wang

Ho Che Yu

Wei-Cheng Lin

Dian-Hau Chen

Chung-Cheng Wu

Wen-Ju Preet Yang

Pin-Dai Sue

Min Cao

Hsiang-Jen Tseng

Hiranmay Biswas

Tzu-Ying Lin

Meng-Hung Shen

Yen-Pin Chen

Jiann-Tyng Tzeng

Yen-Huei Chen

Hung-Jen Liao

Hidehiro Fujiwara

Jonathan Tsung-Yung Chang

Kam-Tou Sio

Yun-Han Lee

Hong-Chen Cheng

Yen-Hung Lin

Meng-Kai Hsu

Chin-Hsiung Hsu

Jyun-Hao Chang

Wei-Ling Chang

Chih-Ming Lai

Shih-Wei Peng

Wen-Chun Huang

Kuo-Ji Chen

Xinyu Bao

Ming-Hsiang Song

Chia-Hung Chu

Shine Chung

Chin-Chang Hsu

Tze-Chiang Huang

Cheng-Chung Lin

Keh-Jeng Chang

Cheng-I Huang

Chia-Hui Chen

Kun-Lung Chen

Yu-Hao Chen

Yen-Sen Wang

Zhe-Wei Jiang

Ming-Zhang Kuo

Ming-Fa Chen

Stefan Rusu

Ming-Feng Shieh

David Barry Scott

Ke-Ying Su

Chii-Ping Chen

Tsong-Hua Ou

Wei-Li Chen

Yao-Ching Ku

Wei-Pin Changchien

Cheng-Hung Yeh

Po-Chia Lai

A semiconductor device includes: a first chip including a plurality of first device features and a plurality of first interconnect structures disposed above the first device features; a second chip including a plurality of second device features and a plurality of second interconnect structures disposed above the second device features; and an interposer bonded to the first chip and the second chip, and disposed on an opposite side from the first and second device features with respect to the first and second interconnect structures; wherein the interposer includes a plurality of power rails configured to deliver power to the first and second chips.

Semiconductor packages and methods of manufacturing thereof

An integrated circuit (IC) includes first through fourth nano-sheet structures extending in a first direction and having respective first through fourth widths along a second direction perpendicular to the first direction, and first through fourth via structures electrically connected to corresponding ones of the first through fourth nano-sheet structures. The second width has a value greater than that of the third width. A width of the second via structure along the second direction has a value greater than that of a width of the third via structure along the second direction. The second and third nano-sheet structures are positioned between the first and fourth nano-sheet structures. The second and third via structures are configured to electrically connect the second and third nano-sheet structures to a first portion of a back-side power distribution structure configured to carry one of a power supply voltage or a reference voltage. The first and fourth via structures are configured to electrically connect the first and fourth nano-sheet structures to a second portion of the back-side power distribution structure configured to carry the other of the power supply voltage or the reference voltage.

Integrated circuit having hybrid sheet structure

A flip-flop circuit includes a first inverter configured to receive a first clock signal and output a second clock signal, a second inverter configured to receive the second clock signal and output a third clock signal, a master latch including a transmission circuit, and a slave latch including a first feedback inverter. The first feedback inverter includes a first transistor configured to receive the first clock signal and a second transistor configured to receive the second clock signal, and the transmission circuit includes a third transistor configured to receive the third clock signal.

Flip-flop circuit and method

A circuit includes a first power node having a first voltage level, a second power node having a second voltage level different from the first voltage level, a reference node having a reference voltage level, a master latch that outputs a first bit based on a received bit, a slave latch that outputs a second bit based on the first bit and an output bit based on a selected one of the first bit or a third bit, a first level shifter that outputs the third bit based on a complementary bit pair, and a retention latch including a second level shifter and a pair of inverters that outputs the complementary bit pair based on the second bit. The slave latch and the first level shifter are coupled between the first power and reference nodes, and the retention latch is coupled between the second power and reference nodes.

Data retention circuit and method

An integrated circuit device includes a device layer having devices spaced in accordance with a predetermined device pitch, a first metal interconnection layer disposed above the device layer and coupled to the device layer, and a second metal interconnection layer disposed above the first metal interconnection layer and coupled to the first metal interconnection layer through a first via layer. The second metal interconnection layer has metal lines spaced in accordance with a predetermined metal line pitch, and a ratio of the predetermined metal line pitch to predetermined device pitch is less than 1.

Integrated circuit device with improved layout

An integrated circuit structure includes a first transistor, a second transistor, a first conductive via, a second conductive via, and a connection line. The first transistor includes a first active region, a first gate electrode over the first active region; and a first channel in the first active region and under the first gate electrode. The second transistor includes a second active region, a second gate electrode over the second active region, and a second channel in the second active region and under the second gate electrode. The first conductive via is electrically connected to the first gate electrode. The second conductive via is electrically connected to the second gate electrode. The connection line electrically connects the first and second conductive vias. The first transistor and the first conductive via and the second transistor and the second conductive via are arranged mirror-symmetrically with respect to a symmetry plane.

Integrated circuit structure and method for manufacturing the same

A method includes fabricating a first-voltage underlayer power rail conductively connecting to the source region of a first-type transistor and fabricating a second-voltage underlayer power rail conductively connecting to the source region of a second-type transistor. Each of the first-voltage and second-voltage underlayer power rails extends in a first direction. The method also includes patterning a first connection layer to form a first-voltage power rail and a second-voltage power rail extending in the second direction which is perpendicular to the first direction. The first-voltage power rail is directly connected with the first-voltage underlayer power rail through a first via-connector and the second-voltage power rail is directly connected with the second-voltage underlayer power rail through a second via-connector.

Power rail and signal conducting line arrangement

An integrated circuit (IC) die includes first through third adjacent rows of through-silicon vias (TSVs), and first and second adjacent rows of memory macros. TSVs of the first row of TSVs extend through and are electrically isolated from memory macros of the first row of memory macros. TSVs of the third row of TSVs extend through and are electrically isolated from memory macros of the second row of memory macros.

Integrated circuit die with memory macro including through-silicon via and method of forming the same

An integrated circuit includes a flip-flop circuit and a gating circuit. The flip-flop circuit is arranged to receive an input data for generating a master signal during a writing mode according to a first clock signal and a second clock signal, and to output an output data according to the first clock signal and the second clock signal during a storing mode. The gating circuit is arranged for generating the first clock signal and the second clock signal according to the master signal and an input clock signal. When the input clock signal is at a signal level, the first clock signal and the second clock signal are at different logic levels. When the input clock signal is at another signal level, the first clock signal and the second clock signal are at a same logic level determined according to a signal level of the master signal.

Flip-flop device and method of operating flip-flop device

An IC structure includes a first cell and a first and second rail. The first cell includes a first and second active region and a first, a second and a third gate structure. The first active region having a first dopant type. The second active region having a second dopant type. The first gate structure extending in a second direction, overlapping the first or the second active region. The second gate structure extending in the second direction, and overlapping a first edge of the first or second active region. The third gate structure extending in the second direction, and overlapping at least a second edge of the first or second active region. The first rail extending in the first direction and overlapping a middle portion of the first active region. The second rail extending in the first direction and overlapping a middle portion of the second active region.

Integrated circuit structure

Packaged semiconductor devices including high-thermal conductivity molding compounds and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a first redistribution structure; a first die over and electrically coupled to the first redistribution structure; a first through via over and electrically coupled to the first redistribution structure; an insulation layer extending along the first redistribution structure, the first die, and the first through via; and an encapsulant over the insulation layer, the encapsulant surrounding portions of the first through via and the first die, the encapsulant including conductive fillers at a concentration ranging from 70% to about 95% by volume.

Semiconductor package having an encapulant comprising conductive fillers and method of manufacture

A method (of generating a layout diagram, the layout diagram being stored on a non-transitory computer-readable medium) includes: selecting first and second standard cells from a standard-cell-library; the first and second standard cells having corresponding first and second heights that are different from each other; stacking the first standard cell on the second standard cell to form a third cell; and including the third cell in a layout diagram. At least one aspect of the method is executed by a processor of a computer.

Different height cell subregions, semiconductor device having the same, and method of generating a layout diagram corresponding to the same

An IC device includes first through third active areas extending in a first direction and a first gate structure extending perpendicular to and overlying each of the first through third active areas. Each of the first through third active areas includes a first portion adjacent to the first gate structure in the first direction and a second portion adjacent to the first portion and including an endpoint of the corresponding active area, the first active area is positioned between the second and third active areas and includes the endpoint positioned under the first gate structure, and each of the second and third active areas includes the endpoint positioned away from the gate structure in a second direction opposite to the first direction.

Integrated circuit device and method

A semiconductor device includes a transistor layer, a first via layer over the transistor layer, a first metallization layer over the first via layer, the first metallization layer including first conductors having long axes extending substantially in a first direction, a second via layer over the first metallization layer, and a conductive deep via extending in the second via layer, the first metallization layer, and the first via layer. The first conductors represent a majority of conductive material in the first metallization layer, and a size of the deep via in the first direction in the first metallization layer is substantially less than a minimum length of the first conductors in the first metallization layer.

Semiconductor device including deep vias

A semiconductor device includes a plurality of standard cells. The plurality of standard cells include a first group of standard cells arranged in a first row extending in a row direction and a second group of standard cells arranged in a second row extending in the row direction. The first group of standard cells and the second group of standard cells are arranged in a column direction. A cell height of the first group of standard cells in the column direction is different from a cell height of the second group of standard cells in the column direction.

Semiconductor device including standard cells

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Taipei, Taiwan

Lee-Chung Lu