Dell Products Inc.

Lee B Zaretsky

Mukund Purshottam Khatri

Isaac Qin Wang

Sompong Paul Olarig

Arnold Thomas Schnell

Srinivas Kamepalli

Shane Michael Chiasson

Roman Szeszycki

Michael S Gatson

Farzad Khosrowpour

Lawrence Edward Knepper

Mitchell Anthony Markow

A clock buffer device for a memory module includes a first clock input coupled to an input of a first phase-locked loop (PLL), and a second clock input coupled to an input of a second PLL. An output of the first PLL is selectably coupled to clock output buffers, and an output of the second PLL is selectably coupled to a subset of the clock output buffers. The clock buffer device receives a first indication that a first information handling system is configured to provide a first clock signal on the first clock input but to not provide a second clock signal on the second clock input, and, in response to the indication, couples the output of the first PLL to the clock output buffers and to disables the second PLL.

Method for power reduction in memory modules

A method of selectively disabling power delivery to a group of memory devices of an information handling system, the method including performing an initialization of a first memory device and a second memory device of the memory devices; after performing the initialization of the memory devices, performing boot procedures at the first memory device and the second memory device; while performing the boot procedures at the first memory device and the second memory device, detecting a memory failure of the first memory device; in response to detecting the memory failure of the first memory device, providing a signal to a power management integrate circuit (PMIC) of the first memory device to disable power at the first memory device; and continuing the boot procedures at the second memory device.

Selectively disabling power delivery to a grouping of memory devices of an information handling system

In one embodiment, a method for increasing power efficiency for an information handling system includes: monitoring, by a host service, one or more performance metrics associated with a memory device of the information handling system, the memory device including a power controller communicably coupled to a management device via a side-band bus; predicting, by the host service, an energy requirement for the memory device based on the one or more performance metrics; generating, by the host service, a power configuration profile based on the energy requirement, the power configuration profile indicating one or more power controller parameters associated with the power controller; sending, by the host service, the power configuration profile to the management device; receiving, by the management device, the power configuration profile; and modifying, by the management device and via the side-band bus, the one or more power controller parameters based on the power configuration profile.

Increasing power efficiency for an information handling system

Methods, systems, and computer programs encoded on computer storage medium, performing, at first time, a calibration and configuration of a data contextual migration model, including: identifying contextual data associated with contextual inputs to a IHS, the contextual data including user contextual data, environmental context data, and system telemetry contextual data; training, based on the contextual data, the data contextual migration model, including: tagging, for each data block of a plurality of data blocks, the data block with identifiers indicating a store location of the data block; storing, based on the identifier associated with each data block, the data block at a local data store of the information handling system, at a remote data store of a remote server computing system, or both; generating a configuration policy including configuration rules, the configuration rules for prioritizing pre-loading of a subset of the data blocks to be provided at the information handling system.

Data contextual migration in an information handling system

A system and method for ensuring information present in volatile memory is moved to persistent memory before power is removed. An information handling system stores a time value corresponding to an amount of time for power to be supplied to the information handling system after a signal is received to power down the information handling system. An embedded controller determines the amount of information present in volatile memory, determines an amount of time needed to move the information to persistent memory, and adjusts the time value as needed to ensure power is supplied to the system until the information has been moved to persistent memory.

System and method for dynamic power control based on a cache size in volatile memory

An information handling system includes a touch sensitive area, which in turn includes an array of pressure sensors and a haptics controller. The array of pressure sensors includes a first pressure sensor. When activated, the first pressure sensor provides an XY location based on a location of the first pressure sensor in the array of pressure sensors. The haptics controller receives an XY location from the first pressure sensor, and a location of a pen device from a pen digitizer circuit. The haptics controller calculates whether the XY location and the location of the pen device are substantially the same location. In response to the XY location and the location of the pen device being substantially the same location, the haptics controller disables haptic feedback within the touch sensitive area.

System and method for dynamically disabling haptic feedback with recognition of pen on touch sensitive area of an information handling system

An information handling system with an improved dynamic application-aware storage optimization includes an application core that is configured to create a plurality of workload descriptors. The workload descriptors may represent workload requirements to implement a particular application program. A data engine performs an analysis of the workload descriptors, and based on the performed analysis the data engine generates a hint. A storage device is configured to use the hint in managing data flow in the information handling system.

Apparatus and method of intelligent dynamic application aware storage device optimization

An information handling system may include a resistive memory buffer to supplement a system main memory unit of the information handling system. A processor of the information handling system may map the resistive memory buffer as system memory, along with the system main memory unit. The processor may use the system memory, including the resistive memory buffer and the system main memory unit in executing one or more applications. The resistive memory buffer may improve performance of the information handling system, such as during hibernation and wake-up processes and memory flush processes.

Storage device buffer in system memory space

In some implementations a logic device, such as an embedded controller, automatically configures a universal serial bus (USB) Type-C port by connecting the USB Type-C port to appropriate input/output (I/O) signals. For example, the logic device may receive a notification that an external device is connected to a USB Type-C port of a computing device. The logic device may receive data from a port controller over an internal communication bus associated with the USB Type-C port. Based at least in part on the data, the logic device may determine one or more types of signals that the external device is configured to send, receive, or send and receive. The logic device may instruct a cross-point switch to connect the USB Type-C port to one or more signal paths in the computing device to enable the external device to send/receive the one or more types of signals.

Automatically configuring a universal serial bus (USB) type-C port of a computing device

Host memory buffer is dynamically adjusted based on performance. As memory pages are accessed, one or more counts of the memory pages are maintained. If the counts indicate some of the memory pages are identical, then a portion of host system memory allocated to buffer cache may be reduced or decremented in response to repetitive access. However, if the counts indicate different memory pages are accessed, then the host system memory allocated to the buffer cache may be increased or incremented.

Dynamically-adjusted host memory buffer

A method for managing the power consumption of an information handling system including a multi-lane serial link having a lane setting that identifies the number of active lanes in the multi-lane serial link. The method may include determining a number of lanes required for the multi-lane serial link based on one or more I/O devices connected to the information handling system, triggering a reduction of the lane setting of the multi-lane serial link if the lane setting of the multi-lane serial link is greater than the determined number of lanes required, and automatically reducing power to the multi-lane serial link in response to the reduction of the lane setting.

Method and apparatus for power throttling of highspeed multi-lane serial links

A method and apparatus for RF access to system identification and fault information is disclosed. In one aspect, the present disclosure teaches a method of accessing system information in an information handling system including storing system information in a computer component forming a part of an information handling system. The method further includes receiving a request for at least a portion of the system information via a radio frequency identification ('RF') transponder link. The method further includes automatically transmitting a response from the computer component via the RFID transponder link such that the response includes the at least a portion of the system information.

Method and apparatus for RF access to system ID and fault information

Determining whether there exists an input-output (I/O) fabric conflict (mismatch) between a blade I/O fabric daughter card of a blade compute module and an I/O interface module of a blade compute module system, and if a conflicts does exit then taking action to correct this I/O fabric mismatch. An I/O fabric router may be coupled between the blade I/O fabric daughter cards and the system I/O interface modules. If a matching I/O interface fabric exists then the I/O fabric router will couple the blade I/O fabric daughter card to the matching I/O interface fabric. If there is no matching I/O interface fabric then the blade I/O fabric daughter card may be decoupled from the blade compute module system so that the associated blade compute module may otherwise function, and an alert may be sent regarding the I/O fabric conflict (absence of an I/O fabric match) for the I/O fabric daughter card of the blade compute module.

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Pflugerville, TX, United States of America

Lee B Zaretsky